Update mdrun-performance.rst

diff --git a/docs/user-guide/mdrun-performance.rst b/docs/user-guide/mdrun-performance.rst
index 09f245547ae3c3752339756fff69c629626c8b37..a394f2e54aa4b2708286fd9092488f0ec7627b65 100644 (file)
--- a/docs/user-guide/mdrun-performance.rst
+++ b/docs/user-guide/mdrun-performance.rst
@@ -213,12 +213,12 @@ of the better clock frequency available. Consider building :ref:`mdrun <gmx mdru
 configured with ``GMX_SIMD=AVX2_256`` instead of ``GMX_SIMD=AVX512`` for better
 performance in GPU accelerated or highly parallel MPI runs.
 
-Some latest ARM based CPU, such as A64fx, support the Scalable Vector Extensions (SVE).
+Some of the latest ARM based CPU, such as the Fujitsu A64fx, support the Scalable Vector Extensions (SVE).
 Though SVE can be used to generate fairly efficient Vector Length Agnostic (VLA) code,
-VLA is not a fit for GROMACS (that currently assumes the SIMD vector length is known at
+this is not a good fit for |Gromacs| (as the SIMD vector length assumed to be known at
 CMake time). Consequently, the SVE vector length must be fixed at CMake time. The default
 value is 512 bits, and this can be changed with ``GMX_SIMD_ARM_SVE_LENGTH=<len>``.
-The supported vector length are 128, 256, 512 and 1024. Since GROMACS optimized non-bonded kernels
+The supported vector lengths are 128, 256, 512 and 1024. Since the SIMD short-range non-bonded kernels
 only support up to 16 floating point numbers per SIMD vector, 1024 bits vector length is only
 valid in double precision (e.g. ``-DGMX_DOUBLE=on``).
 Note that even if `mdrun` does check the SIMD vector length at runtime, running with a different