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37 #include "gromacs/legacyheaders/gmx_cpuid.h"
48 #ifdef GMX_NATIVE_WINDOWS
49 /* MSVC definition for __cpuid() */
53 /* sysinfo functions */
60 /* sysconf() definition */
65 /* For convenience, and to enable configure-time invocation, we keep all architectures
66 * in a single file, but to avoid repeated ifdefs we set the overall architecture here.
69 /* OK, it is x86, but can we execute cpuid? */
70 #if defined(GMX_X86_GCC_INLINE_ASM) || ( defined(_MSC_VER) && ( (_MSC_VER > 1500) || (_MSC_VER == 1500 & _MSC_FULL_VER >= 150030729)))
71 # define GMX_CPUID_X86
75 /* Global constant character strings corresponding to our enumerated types */
77 gmx_cpuid_vendor_string[GMX_CPUID_NVENDORS] =
84 "IBM", /* Used on Power and BlueGene/Q */
89 gmx_cpuid_vendor_string_alternative[GMX_CPUID_NVENDORS] =
96 "ibm", /* Used on Power and BlueGene/Q */
101 gmx_cpuid_feature_string[GMX_CPUID_NFEATURES] =
145 gmx_cpuid_simd_string[GMX_CPUID_NSIMD] =
162 /* Max length of brand string */
163 #define GMX_CPUID_STRLEN 256
166 /* Contents of the abstract datatype */
169 enum gmx_cpuid_vendor vendor;
170 char brand[GMX_CPUID_STRLEN];
174 /* Not using gmx_bool here, since this file must be possible to compile without simple.h */
175 char feature[GMX_CPUID_NFEATURES];
177 /* Basic CPU topology information. For x86 this is a bit complicated since the topology differs between
178 * operating systems and sometimes even settings. For most other architectures you can likely just check
179 * the documentation and then write static information to these arrays rather than detecting on-the-fly.
181 int have_cpu_topology;
182 int nproc; /* total number of logical processors from OS */
184 int ncores_per_package;
185 int nhwthreads_per_core;
187 int * core_id; /* Local core id in each package */
188 int * hwthread_id; /* Local hwthread id in each core */
189 int * locality_order; /* Processor indices sorted in locality order */
193 /* Simple routines to access the data structure. The initialization routine is
194 * further down since that needs to call other static routines in this file.
196 enum gmx_cpuid_vendor
197 gmx_cpuid_vendor (gmx_cpuid_t cpuid)
199 return cpuid->vendor;
204 gmx_cpuid_brand (gmx_cpuid_t cpuid)
210 gmx_cpuid_family (gmx_cpuid_t cpuid)
212 return cpuid->family;
216 gmx_cpuid_model (gmx_cpuid_t cpuid)
222 gmx_cpuid_stepping (gmx_cpuid_t cpuid)
224 return cpuid->stepping;
228 gmx_cpuid_feature (gmx_cpuid_t cpuid,
229 enum gmx_cpuid_feature feature)
231 return (cpuid->feature[feature] != 0);
237 /* What type of SIMD was compiled in, if any? */
238 #ifdef GMX_SIMD_X86_AVX2_256
239 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_X86_AVX2_256;
240 #elif defined GMX_SIMD_X86_AVX_256
241 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_X86_AVX_256;
242 #elif defined GMX_SIMD_X86_AVX_128_FMA
243 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_X86_AVX_128_FMA;
244 #elif defined GMX_SIMD_X86_SSE4_1
245 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_X86_SSE4_1;
246 #elif defined GMX_SIMD_X86_SSE2
247 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_X86_SSE2;
248 #elif defined GMX_SIMD_ARM_NEON
249 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_ARM_NEON;
250 #elif defined GMX_SIMD_ARM_NEON_ASIMD
251 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_ARM_NEON_ASIMD;
252 #elif defined GMX_SIMD_SPARC64_HPC_ACE
253 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_SPARC64_HPC_ACE;
254 #elif defined GMX_SIMD_IBM_QPX
255 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_IBM_QPX;
256 #elif defined GMX_SIMD_IBM_VMX
257 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_IBM_VMX;
258 #elif defined GMX_SIMD_REFERENCE
259 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_REFERENCE;
261 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_NONE;
267 /* Execute CPUID on x86 class CPUs. level sets function to exec, and the
268 * contents of register output is returned. See Intel/AMD docs for details.
270 * This version supports extended information where we can also have an input
271 * value in the ecx register. This is ignored for most levels, but some of them
272 * (e.g. level 0xB on Intel) use it.
275 execute_x86cpuid(unsigned int level,
284 /* Currently CPUID is only supported (1) if we can use an instruction on MSVC, or (2)
285 * if the compiler handles GNU-style inline assembly.
288 #if (defined _MSC_VER)
291 #if (_MSC_VER > 1500) || (_MSC_VER == 1500 & _MSC_FULL_VER >= 150030729)
292 /* MSVC 9.0 SP1 or later */
293 __cpuidex(CPUInfo, level, ecxval);
296 __cpuid(CPUInfo, level);
297 /* Set an error code if the user wanted a non-zero ecxval, since we did not have cpuidex */
298 rc = (ecxval > 0) ? -1 : 0;
305 #elif (defined GMX_X86_GCC_INLINE_ASM)
306 /* for now this means GMX_X86_GCC_INLINE_ASM should be defined,
307 * but there might be more options added in the future.
313 #if defined(__i386__) && defined(__PIC__)
314 /* Avoid clobbering the global offset table in 32-bit pic code (ebx register) */
315 __asm__ __volatile__ ("xchgl %%ebx, %1 \n\t"
317 "xchgl %%ebx, %1 \n\t"
318 : "+a" (*eax), "+r" (*ebx), "+c" (*ecx), "+d" (*edx));
320 /* i386 without PIC, or x86-64. Things are easy and we can clobber any reg we want :-) */
321 __asm__ __volatile__ ("cpuid \n\t"
322 : "+a" (*eax), "+b" (*ebx), "+c" (*ecx), "+d" (*edx));
327 * Apparently this is an x86 platform where we don't know how to call cpuid.
329 * This is REALLY bad, since we will lose all Gromacs SIMD support.
342 /* Identify CPU features common to Intel & AMD - mainly brand string,
343 * version and some features. Vendor has already been detected outside this.
346 cpuid_check_common_x86(gmx_cpuid_t cpuid)
348 int fn, max_stdfn, max_extfn;
349 unsigned int eax, ebx, ecx, edx;
350 char str[GMX_CPUID_STRLEN];
353 /* Find largest standard/extended function input value */
354 execute_x86cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
356 execute_x86cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
360 if (max_extfn >= 0x80000005)
362 /* Get CPU brand string */
363 for (fn = 0x80000002; fn < 0x80000005; fn++)
365 execute_x86cpuid(fn, 0, &eax, &ebx, &ecx, &edx);
367 memcpy(p+4, &ebx, 4);
368 memcpy(p+8, &ecx, 4);
369 memcpy(p+12, &edx, 4);
374 /* Remove empty initial space */
376 while (isspace(*(p)))
380 strncpy(cpuid->brand, p, GMX_CPUID_STRLEN);
384 strncpy(cpuid->brand, "Unknown CPU brand", GMX_CPUID_STRLEN);
387 /* Find basic CPU properties */
390 execute_x86cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
392 cpuid->family = ((eax & 0x0FF00000) >> 20) + ((eax & 0x00000F00) >> 8);
393 /* Note that extended model should be shifted left 4, so only shift right 12 iso 16. */
394 cpuid->model = ((eax & 0x000F0000) >> 12) + ((eax & 0x000000F0) >> 4);
395 cpuid->stepping = (eax & 0x0000000F);
397 /* Feature flags common to AMD and intel */
398 cpuid->feature[GMX_CPUID_FEATURE_X86_SSE3] = (ecx & (1 << 0)) != 0;
399 cpuid->feature[GMX_CPUID_FEATURE_X86_PCLMULDQ] = (ecx & (1 << 1)) != 0;
400 cpuid->feature[GMX_CPUID_FEATURE_X86_SSSE3] = (ecx & (1 << 9)) != 0;
401 cpuid->feature[GMX_CPUID_FEATURE_X86_FMA] = (ecx & (1 << 12)) != 0;
402 cpuid->feature[GMX_CPUID_FEATURE_X86_CX16] = (ecx & (1 << 13)) != 0;
403 cpuid->feature[GMX_CPUID_FEATURE_X86_SSE4_1] = (ecx & (1 << 19)) != 0;
404 cpuid->feature[GMX_CPUID_FEATURE_X86_SSE4_2] = (ecx & (1 << 20)) != 0;
405 cpuid->feature[GMX_CPUID_FEATURE_X86_POPCNT] = (ecx & (1 << 23)) != 0;
406 cpuid->feature[GMX_CPUID_FEATURE_X86_AES] = (ecx & (1 << 25)) != 0;
407 cpuid->feature[GMX_CPUID_FEATURE_X86_AVX] = (ecx & (1 << 28)) != 0;
408 cpuid->feature[GMX_CPUID_FEATURE_X86_F16C] = (ecx & (1 << 29)) != 0;
409 cpuid->feature[GMX_CPUID_FEATURE_X86_RDRND] = (ecx & (1 << 30)) != 0;
411 cpuid->feature[GMX_CPUID_FEATURE_X86_PSE] = (edx & (1 << 3)) != 0;
412 cpuid->feature[GMX_CPUID_FEATURE_X86_MSR] = (edx & (1 << 5)) != 0;
413 cpuid->feature[GMX_CPUID_FEATURE_X86_CX8] = (edx & (1 << 8)) != 0;
414 cpuid->feature[GMX_CPUID_FEATURE_X86_APIC] = (edx & (1 << 9)) != 0;
415 cpuid->feature[GMX_CPUID_FEATURE_X86_CMOV] = (edx & (1 << 15)) != 0;
416 cpuid->feature[GMX_CPUID_FEATURE_X86_CLFSH] = (edx & (1 << 19)) != 0;
417 cpuid->feature[GMX_CPUID_FEATURE_X86_MMX] = (edx & (1 << 23)) != 0;
418 cpuid->feature[GMX_CPUID_FEATURE_X86_SSE2] = (edx & (1 << 26)) != 0;
419 cpuid->feature[GMX_CPUID_FEATURE_X86_HTT] = (edx & (1 << 28)) != 0;
425 cpuid->stepping = -1;
428 if (max_extfn >= 0x80000001)
430 execute_x86cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
431 cpuid->feature[GMX_CPUID_FEATURE_X86_LAHF_LM] = (ecx & (1 << 0)) != 0;
432 cpuid->feature[GMX_CPUID_FEATURE_X86_PDPE1GB] = (edx & (1 << 26)) != 0;
433 cpuid->feature[GMX_CPUID_FEATURE_X86_RDTSCP] = (edx & (1 << 27)) != 0;
436 if (max_extfn >= 0x80000007)
438 execute_x86cpuid(0x80000007, 0, &eax, &ebx, &ecx, &edx);
439 cpuid->feature[GMX_CPUID_FEATURE_X86_NONSTOP_TSC] = (edx & (1 << 8)) != 0;
444 /* This routine returns the number of unique different elements found in the array,
445 * and renumbers these starting from 0. For example, the array {0,1,2,8,9,10,8,9,10,0,1,2}
446 * will be rewritten to {0,1,2,3,4,5,3,4,5,0,1,2}, and it returns 6 for the
447 * number of unique elements.
450 cpuid_renumber_elements(int *data, int n)
453 int i, j, nunique, found;
455 unique = malloc(sizeof(int)*n);
458 for (i = 0; i < n; i++)
460 for (j = 0, found = 0; j < nunique && !found; j++)
462 found = (data[i] == unique[j]);
466 /* Insert in sorted order! */
467 for (j = nunique++; j > 0 && unique[j-1] > data[i]; j--)
469 unique[j] = unique[j-1];
475 for (i = 0; i < n; i++)
477 for (j = 0; j < nunique; j++)
479 if (data[i] == unique[j])
489 /* APIC IDs, or everything you wanted to know about your x86 cores but were afraid to ask...
491 * Raw APIC IDs are unfortunately somewhat dirty. For technical reasons they are assigned
492 * in power-of-2 chunks, and even then there are no guarantees about specific numbers - all
493 * we know is that the part for each thread/core/package is unique, and how many bits are
494 * reserved for that part.
495 * This routine does internal renumbering so we get continuous indices, and also
496 * decodes the actual number of packages,cores-per-package and hwthreads-per-core.
497 * Returns: 0 on success, non-zero on failure.
500 cpuid_x86_decode_apic_id(gmx_cpuid_t cpuid, int *apic_id, int core_bits, int hwthread_bits)
503 int hwthread_mask, core_mask_after_shift;
505 cpuid->hwthread_id = malloc(sizeof(int)*cpuid->nproc);
506 cpuid->core_id = malloc(sizeof(int)*cpuid->nproc);
507 cpuid->package_id = malloc(sizeof(int)*cpuid->nproc);
508 cpuid->locality_order = malloc(sizeof(int)*cpuid->nproc);
510 hwthread_mask = (1 << hwthread_bits) - 1;
511 core_mask_after_shift = (1 << core_bits) - 1;
513 for (i = 0; i < cpuid->nproc; i++)
515 cpuid->hwthread_id[i] = apic_id[i] & hwthread_mask;
516 cpuid->core_id[i] = (apic_id[i] >> hwthread_bits) & core_mask_after_shift;
517 cpuid->package_id[i] = apic_id[i] >> (core_bits + hwthread_bits);
520 cpuid->npackages = cpuid_renumber_elements(cpuid->package_id, cpuid->nproc);
521 cpuid->ncores_per_package = cpuid_renumber_elements(cpuid->core_id, cpuid->nproc);
522 cpuid->nhwthreads_per_core = cpuid_renumber_elements(cpuid->hwthread_id, cpuid->nproc);
524 /* now check for consistency */
525 if ( (cpuid->npackages * cpuid->ncores_per_package *
526 cpuid->nhwthreads_per_core) != cpuid->nproc)
528 /* the packages/cores-per-package/hwthreads-per-core counts are
533 /* Create a locality order array, i.e. first all resources in package0, which in turn
534 * are sorted so we first have all resources in core0, where threads are sorted in order, etc.
537 for (i = 0; i < cpuid->nproc; i++)
539 idx = (cpuid->package_id[i]*cpuid->ncores_per_package + cpuid->core_id[i])*cpuid->nhwthreads_per_core + cpuid->hwthread_id[i];
540 cpuid->locality_order[idx] = i;
546 /* Detection of AMD-specific CPU features */
548 cpuid_check_amd_x86(gmx_cpuid_t cpuid)
550 int max_stdfn, max_extfn, ret;
551 unsigned int eax, ebx, ecx, edx;
552 int hwthread_bits, core_bits;
555 cpuid_check_common_x86(cpuid);
557 execute_x86cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
560 execute_x86cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
563 if (max_extfn >= 0x80000001)
565 execute_x86cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
567 cpuid->feature[GMX_CPUID_FEATURE_X86_SSE4A] = (ecx & (1 << 6)) != 0;
568 cpuid->feature[GMX_CPUID_FEATURE_X86_MISALIGNSSE] = (ecx & (1 << 7)) != 0;
569 cpuid->feature[GMX_CPUID_FEATURE_X86_XOP] = (ecx & (1 << 11)) != 0;
570 cpuid->feature[GMX_CPUID_FEATURE_X86_FMA4] = (ecx & (1 << 16)) != 0;
573 /* Query APIC information on AMD */
574 if (max_extfn >= 0x80000008)
576 #if (defined HAVE_SCHED_AFFINITY && defined HAVE_SYSCONF && defined __linux__)
579 cpu_set_t cpuset, save_cpuset;
580 cpuid->nproc = sysconf(_SC_NPROCESSORS_ONLN);
581 apic_id = malloc(sizeof(int)*cpuid->nproc);
582 sched_getaffinity(0, sizeof(cpu_set_t), &save_cpuset);
583 /* Get APIC id from each core */
585 for (i = 0; i < cpuid->nproc; i++)
588 sched_setaffinity(0, sizeof(cpu_set_t), &cpuset);
589 execute_x86cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
590 apic_id[i] = ebx >> 24;
593 /* Reset affinity to the value it had when calling this routine */
594 sched_setaffinity(0, sizeof(cpu_set_t), &save_cpuset);
595 #define CPUID_HAVE_APIC
596 #elif defined GMX_NATIVE_WINDOWS
600 unsigned int save_affinity, affinity;
601 GetSystemInfo( &sysinfo );
602 cpuid->nproc = sysinfo.dwNumberOfProcessors;
603 apic_id = malloc(sizeof(int)*cpuid->nproc);
604 /* Get previous affinity mask */
605 save_affinity = SetThreadAffinityMask(GetCurrentThread(), 1);
606 for (i = 0; i < cpuid->nproc; i++)
608 SetThreadAffinityMask(GetCurrentThread(), (((DWORD_PTR)1)<<i));
610 execute_x86cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
611 apic_id[i] = ebx >> 24;
613 SetThreadAffinityMask(GetCurrentThread(), save_affinity);
614 #define CPUID_HAVE_APIC
616 #ifdef CPUID_HAVE_APIC
617 /* AMD does not support SMT yet - there are no hwthread bits in apic ID */
619 /* Get number of core bits in apic ID - try modern extended method first */
620 execute_x86cpuid(0x80000008, 0, &eax, &ebx, &ecx, &edx);
621 core_bits = (ecx >> 12) & 0xf;
624 /* Legacy method for old single/dual core AMD CPUs */
626 for (core_bits = 0; (i>>core_bits) > 0; core_bits++)
631 ret = cpuid_x86_decode_apic_id(cpuid, apic_id, core_bits,
633 cpuid->have_cpu_topology = (ret == 0);
639 /* Detection of Intel-specific CPU features */
641 cpuid_check_intel_x86(gmx_cpuid_t cpuid)
643 unsigned int max_stdfn, max_extfn, ret;
644 unsigned int eax, ebx, ecx, edx;
645 unsigned int max_logical_cores, max_physical_cores;
646 int hwthread_bits, core_bits;
649 cpuid_check_common_x86(cpuid);
651 execute_x86cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
654 execute_x86cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
659 execute_x86cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
660 cpuid->feature[GMX_CPUID_FEATURE_X86_PDCM] = (ecx & (1 << 15)) != 0;
661 cpuid->feature[GMX_CPUID_FEATURE_X86_PCID] = (ecx & (1 << 17)) != 0;
662 cpuid->feature[GMX_CPUID_FEATURE_X86_X2APIC] = (ecx & (1 << 21)) != 0;
663 cpuid->feature[GMX_CPUID_FEATURE_X86_TDT] = (ecx & (1 << 24)) != 0;
668 execute_x86cpuid(0x7, 0, &eax, &ebx, &ecx, &edx);
669 cpuid->feature[GMX_CPUID_FEATURE_X86_AVX2] = (ebx & (1 << 5)) != 0;
672 /* Check whether Hyper-Threading is enabled, not only supported */
673 if (cpuid->feature[GMX_CPUID_FEATURE_X86_HTT] && max_stdfn >= 4)
675 execute_x86cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
676 max_logical_cores = (ebx >> 16) & 0x0FF;
677 execute_x86cpuid(0x4, 0, &eax, &ebx, &ecx, &edx);
678 max_physical_cores = ((eax >> 26) & 0x3F) + 1;
680 /* Clear HTT flag if we only have 1 logical core per physical */
681 if (max_logical_cores/max_physical_cores < 2)
683 cpuid->feature[GMX_CPUID_FEATURE_X86_HTT] = 0;
687 if (max_stdfn >= 0xB)
689 /* Query x2 APIC information from cores */
690 #if (defined HAVE_SCHED_AFFINITY && defined HAVE_SYSCONF && defined __linux__)
693 cpu_set_t cpuset, save_cpuset;
694 cpuid->nproc = sysconf(_SC_NPROCESSORS_ONLN);
695 apic_id = malloc(sizeof(int)*cpuid->nproc);
696 sched_getaffinity(0, sizeof(cpu_set_t), &save_cpuset);
697 /* Get x2APIC ID from each hardware thread */
699 for (i = 0; i < cpuid->nproc; i++)
702 sched_setaffinity(0, sizeof(cpu_set_t), &cpuset);
703 execute_x86cpuid(0xB, 0, &eax, &ebx, &ecx, &edx);
707 /* Reset affinity to the value it had when calling this routine */
708 sched_setaffinity(0, sizeof(cpu_set_t), &save_cpuset);
709 #define CPUID_HAVE_APIC
710 #elif defined GMX_NATIVE_WINDOWS
714 unsigned int save_affinity, affinity;
715 GetSystemInfo( &sysinfo );
716 cpuid->nproc = sysinfo.dwNumberOfProcessors;
717 apic_id = malloc(sizeof(int)*cpuid->nproc);
718 /* Get previous affinity mask */
719 save_affinity = SetThreadAffinityMask(GetCurrentThread(), 1);
720 for (i = 0; i < cpuid->nproc; i++)
722 SetThreadAffinityMask(GetCurrentThread(), (((DWORD_PTR)1)<<i));
724 execute_x86cpuid(0xB, 0, &eax, &ebx, &ecx, &edx);
727 SetThreadAffinityMask(GetCurrentThread(), save_affinity);
728 #define CPUID_HAVE_APIC
730 #ifdef CPUID_HAVE_APIC
731 execute_x86cpuid(0xB, 0, &eax, &ebx, &ecx, &edx);
732 hwthread_bits = eax & 0x1F;
733 execute_x86cpuid(0xB, 1, &eax, &ebx, &ecx, &edx);
734 core_bits = (eax & 0x1F) - hwthread_bits;
735 ret = cpuid_x86_decode_apic_id(cpuid, apic_id, core_bits,
737 cpuid->have_cpu_topology = (ret == 0);
742 #endif /* GMX_CPUID_X86 */
747 chomp_substring_before_colon(const char *in, char *s, int maxlength)
750 strncpy(s, in, maxlength);
755 while (isspace(*(--p)) && (p >= s))
767 chomp_substring_after_colon(const char *in, char *s, int maxlength)
770 if ( (p = strchr(in, ':')) != NULL)
777 strncpy(s, p, maxlength);
779 while (isspace(*(--p)) && (p >= s))
791 cpuid_check_arm(gmx_cpuid_t cpuid)
793 #if defined(__linux__) || defined(__linux)
795 char buffer[GMX_CPUID_STRLEN], buffer2[GMX_CPUID_STRLEN], buffer3[GMX_CPUID_STRLEN];
797 if ( (fp = fopen("/proc/cpuinfo", "r")) != NULL)
799 while ( (fgets(buffer, sizeof(buffer), fp) != NULL))
801 chomp_substring_before_colon(buffer, buffer2, GMX_CPUID_STRLEN);
802 chomp_substring_after_colon(buffer, buffer3, GMX_CPUID_STRLEN);
804 if (!strcmp(buffer2, "Processor"))
806 strncpy(cpuid->brand, buffer3, GMX_CPUID_STRLEN);
808 else if (!strcmp(buffer2, "CPU architecture"))
810 cpuid->family = strtol(buffer3, NULL, 10);
811 if (!strcmp(buffer3, "AArch64"))
816 else if (!strcmp(buffer2, "CPU part"))
818 cpuid->model = strtol(buffer3, NULL, 16);
820 else if (!strcmp(buffer2, "CPU revision"))
822 cpuid->stepping = strtol(buffer3, NULL, 10);
824 else if (!strcmp(buffer2, "Features") && strstr(buffer3, "neon"))
826 cpuid->feature[GMX_CPUID_FEATURE_ARM_NEON] = 1;
828 else if (!strcmp(buffer2, "Features") && strstr(buffer3, "asimd"))
830 cpuid->feature[GMX_CPUID_FEATURE_ARM_NEON_ASIMD] = 1;
837 /* Strange 64-bit non-linux platform. However, since NEON ASIMD is present on all
838 * implementations of AArch64 this far, we assume it is present for now.
840 cpuid->feature[GMX_CPUID_FEATURE_ARM_NEON_ASIMD] = 1;
842 /* Strange 32-bit non-linux platform. We cannot assume that neon is present. */
843 cpuid->feature[GMX_CPUID_FEATURE_ARM_NEON] = 0;
851 cpuid_check_ibm(gmx_cpuid_t cpuid)
853 #if defined(__linux__) || defined(__linux)
855 char buffer[GMX_CPUID_STRLEN], before_colon[GMX_CPUID_STRLEN], after_colon[GMX_CPUID_STRLEN];
857 if ( (fp = fopen("/proc/cpuinfo", "r")) != NULL)
859 while ( (fgets(buffer, sizeof(buffer), fp) != NULL))
861 chomp_substring_before_colon(buffer, before_colon, GMX_CPUID_STRLEN);
862 chomp_substring_after_colon(buffer, after_colon, GMX_CPUID_STRLEN);
864 if (!strcmp(before_colon, "model name") ||
865 !strcmp(before_colon, "model") ||
866 !strcmp(before_colon, "Processor") ||
867 !strcmp(before_colon, "cpu"))
869 strncpy(cpuid->brand, after_colon, GMX_CPUID_STRLEN);
871 if (strstr(after_colon, "altivec"))
873 cpuid->feature[GMX_CPUID_FEATURE_IBM_VMX] = 1;
880 if (strstr(cpuid->brand, "A2"))
883 cpuid->feature[GMX_CPUID_FEATURE_IBM_QPX] = 1;
886 strncpy(cpuid->brand, "Unknown CPU brand", GMX_CPUID_STRLEN);
887 cpuid->feature[GMX_CPUID_FEATURE_IBM_QPX] = 0;
888 cpuid->feature[GMX_CPUID_FEATURE_IBM_VMX] = 0;
894 /* Try to find the vendor of the current CPU, so we know what specific
895 * detection routine to call.
897 static enum gmx_cpuid_vendor
898 cpuid_check_vendor(void)
900 enum gmx_cpuid_vendor i, vendor;
901 /* Register data used on x86 */
902 unsigned int eax, ebx, ecx, edx;
903 char vendorstring[13];
905 char buffer[GMX_CPUID_STRLEN];
906 char before_colon[GMX_CPUID_STRLEN];
907 char after_colon[GMX_CPUID_STRLEN];
909 /* Set default first */
910 vendor = GMX_CPUID_VENDOR_UNKNOWN;
913 execute_x86cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
915 memcpy(vendorstring, &ebx, 4);
916 memcpy(vendorstring+4, &edx, 4);
917 memcpy(vendorstring+8, &ecx, 4);
919 vendorstring[12] = '\0';
921 for (i = GMX_CPUID_VENDOR_UNKNOWN; i < GMX_CPUID_NVENDORS; i++)
923 if (!strncmp(vendorstring, gmx_cpuid_vendor_string[i], 12))
928 #elif defined(__linux__) || defined(__linux)
929 /* General Linux. Try to get CPU vendor from /proc/cpuinfo */
930 if ( (fp = fopen("/proc/cpuinfo", "r")) != NULL)
932 while ( (vendor == GMX_CPUID_VENDOR_UNKNOWN) && (fgets(buffer, sizeof(buffer), fp) != NULL))
934 chomp_substring_before_colon(buffer, before_colon, sizeof(before_colon));
935 /* Intel/AMD use "vendor_id", IBM "vendor", "model", or "cpu". Fujitsu "manufacture".
936 * On ARM there does not seem to be a vendor, but ARM or AArch64 is listed in the Processor string.
937 * Add others if you have them!
939 if (!strcmp(before_colon, "vendor_id")
940 || !strcmp(before_colon, "vendor")
941 || !strcmp(before_colon, "manufacture")
942 || !strcmp(before_colon, "model")
943 || !strcmp(before_colon, "Processor")
944 || !strcmp(before_colon, "cpu"))
946 chomp_substring_after_colon(buffer, after_colon, sizeof(after_colon));
947 for (i = GMX_CPUID_VENDOR_UNKNOWN; i < GMX_CPUID_NVENDORS; i++)
949 /* Be liberal and accept if we find the vendor
950 * string (or alternative string) anywhere. Using
951 * strcasestr() would be non-portable. */
952 if (strstr(after_colon, gmx_cpuid_vendor_string[i])
953 || strstr(after_colon, gmx_cpuid_vendor_string_alternative[i]))
958 /* If we did not find vendor yet, check if it is IBM:
959 * On some Power/PowerPC systems it only says power, not IBM.
961 if (vendor == GMX_CPUID_VENDOR_UNKNOWN &&
962 ((strstr(after_colon, "POWER") || strstr(after_colon, "Power") ||
963 strstr(after_colon, "power"))))
965 vendor = GMX_CPUID_VENDOR_IBM;
971 #elif defined(__arm__) || defined (__arm) || defined(__aarch64__)
972 /* If we are using ARM on something that is not linux we have to trust the compiler,
973 * and we cannot get the extra info that might be present in /proc/cpuinfo.
975 vendor = GMX_CPUID_VENDOR_ARM;
983 gmx_cpuid_topology(gmx_cpuid_t cpuid,
986 int * ncores_per_package,
987 int * nhwthreads_per_core,
988 const int ** package_id,
989 const int ** core_id,
990 const int ** hwthread_id,
991 const int ** locality_order)
995 if (cpuid->have_cpu_topology)
997 *nprocessors = cpuid->nproc;
998 *npackages = cpuid->npackages;
999 *ncores_per_package = cpuid->ncores_per_package;
1000 *nhwthreads_per_core = cpuid->nhwthreads_per_core;
1001 *package_id = cpuid->package_id;
1002 *core_id = cpuid->core_id;
1003 *hwthread_id = cpuid->hwthread_id;
1004 *locality_order = cpuid->locality_order;
1015 enum gmx_cpuid_x86_smt
1016 gmx_cpuid_x86_smt(gmx_cpuid_t cpuid)
1018 enum gmx_cpuid_x86_smt rc;
1020 if (cpuid->have_cpu_topology)
1022 rc = (cpuid->nhwthreads_per_core > 1) ? GMX_CPUID_X86_SMT_ENABLED : GMX_CPUID_X86_SMT_DISABLED;
1024 else if (cpuid->vendor == GMX_CPUID_VENDOR_AMD || gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_HTT) == 0)
1026 rc = GMX_CPUID_X86_SMT_DISABLED;
1030 rc = GMX_CPUID_X86_SMT_CANNOTDETECT;
1037 gmx_cpuid_init (gmx_cpuid_t * pcpuid)
1042 char buffer[GMX_CPUID_STRLEN], buffer2[GMX_CPUID_STRLEN];
1045 cpuid = malloc(sizeof(*cpuid));
1049 for (i = 0; i < GMX_CPUID_NFEATURES; i++)
1051 cpuid->feature[i] = 0;
1054 cpuid->have_cpu_topology = 0;
1056 cpuid->npackages = 0;
1057 cpuid->ncores_per_package = 0;
1058 cpuid->nhwthreads_per_core = 0;
1059 cpuid->package_id = NULL;
1060 cpuid->core_id = NULL;
1061 cpuid->hwthread_id = NULL;
1062 cpuid->locality_order = NULL;
1064 cpuid->vendor = cpuid_check_vendor();
1066 switch (cpuid->vendor)
1068 #ifdef GMX_CPUID_X86
1069 case GMX_CPUID_VENDOR_INTEL:
1070 cpuid_check_intel_x86(cpuid);
1072 case GMX_CPUID_VENDOR_AMD:
1073 cpuid_check_amd_x86(cpuid);
1076 case GMX_CPUID_VENDOR_ARM:
1077 cpuid_check_arm(cpuid);
1079 case GMX_CPUID_VENDOR_IBM:
1080 cpuid_check_ibm(cpuid);
1084 strncpy(cpuid->brand, "Unknown CPU brand", GMX_CPUID_STRLEN);
1085 #if defined(__linux__) || defined(__linux)
1086 /* General Linux. Try to get CPU type from /proc/cpuinfo */
1087 if ( (fp = fopen("/proc/cpuinfo", "r")) != NULL)
1090 while ( (found_brand == 0) && (fgets(buffer, sizeof(buffer), fp) != NULL))
1092 chomp_substring_before_colon(buffer, buffer2, sizeof(buffer2));
1093 /* Intel uses "model name", Fujitsu and IBM "cpu". */
1094 if (!strcmp(buffer2, "model name") || !strcmp(buffer2, "cpu"))
1096 chomp_substring_after_colon(buffer, cpuid->brand, GMX_CPUID_STRLEN);
1105 cpuid->stepping = 0;
1107 for (i = 0; i < GMX_CPUID_NFEATURES; i++)
1109 cpuid->feature[i] = 0;
1111 cpuid->feature[GMX_CPUID_FEATURE_CANNOTDETECT] = 1;
1120 gmx_cpuid_done (gmx_cpuid_t cpuid)
1127 gmx_cpuid_formatstring (gmx_cpuid_t cpuid,
1133 enum gmx_cpuid_feature feature;
1139 "Family: %2d Model: %2d Stepping: %2d\n"
1141 gmx_cpuid_vendor_string[gmx_cpuid_vendor(cpuid)],
1142 gmx_cpuid_brand(cpuid),
1143 gmx_cpuid_family(cpuid), gmx_cpuid_model(cpuid), gmx_cpuid_stepping(cpuid));
1148 "Family: %2d Model: %2d Stepping: %2d\n"
1150 gmx_cpuid_vendor_string[gmx_cpuid_vendor(cpuid)],
1151 gmx_cpuid_brand(cpuid),
1152 gmx_cpuid_family(cpuid), gmx_cpuid_model(cpuid), gmx_cpuid_stepping(cpuid));
1160 for (feature = GMX_CPUID_FEATURE_CANNOTDETECT; feature < GMX_CPUID_NFEATURES; feature++)
1162 if (gmx_cpuid_feature(cpuid, feature) == 1)
1165 _snprintf(str, n, " %s", gmx_cpuid_feature_string[feature]);
1167 snprintf(str, n, " %s", gmx_cpuid_feature_string[feature]);
1176 _snprintf(str, n, "\n");
1178 snprintf(str, n, "\n");
1188 gmx_cpuid_simd_suggest (gmx_cpuid_t cpuid)
1190 enum gmx_cpuid_simd tmpsimd;
1192 tmpsimd = GMX_CPUID_SIMD_NONE;
1194 if (gmx_cpuid_vendor(cpuid) == GMX_CPUID_VENDOR_INTEL)
1196 if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_AVX2))
1198 tmpsimd = GMX_CPUID_SIMD_X86_AVX2_256;
1200 else if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_AVX))
1202 tmpsimd = GMX_CPUID_SIMD_X86_AVX_256;
1204 else if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_SSE4_1))
1206 tmpsimd = GMX_CPUID_SIMD_X86_SSE4_1;
1208 else if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_SSE2))
1210 tmpsimd = GMX_CPUID_SIMD_X86_SSE2;
1213 else if (gmx_cpuid_vendor(cpuid) == GMX_CPUID_VENDOR_AMD)
1215 if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_AVX))
1217 tmpsimd = GMX_CPUID_SIMD_X86_AVX_128_FMA;
1219 else if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_SSE4_1))
1221 tmpsimd = GMX_CPUID_SIMD_X86_SSE4_1;
1223 else if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_SSE2))
1225 tmpsimd = GMX_CPUID_SIMD_X86_SSE2;
1228 else if (gmx_cpuid_vendor(cpuid) == GMX_CPUID_VENDOR_FUJITSU)
1230 if (strstr(gmx_cpuid_brand(cpuid), "SPARC64"))
1232 tmpsimd = GMX_CPUID_SIMD_SPARC64_HPC_ACE;
1235 else if (gmx_cpuid_vendor(cpuid) == GMX_CPUID_VENDOR_IBM)
1237 if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_IBM_QPX))
1239 tmpsimd = GMX_CPUID_SIMD_IBM_QPX;
1241 else if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_IBM_VMX))
1243 tmpsimd = GMX_CPUID_SIMD_IBM_VMX;
1246 else if (gmx_cpuid_vendor(cpuid) == GMX_CPUID_VENDOR_ARM)
1248 if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_ARM_NEON_ASIMD))
1250 tmpsimd = GMX_CPUID_SIMD_ARM_NEON_ASIMD;
1252 else if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_ARM_NEON))
1254 tmpsimd = GMX_CPUID_SIMD_ARM_NEON;
1263 gmx_cpuid_simd_check(gmx_cpuid_t cpuid,
1265 int print_to_stderr)
1269 enum gmx_cpuid_simd simd;
1271 simd = gmx_cpuid_simd_suggest(cpuid);
1273 rc = (simd != compiled_simd);
1275 gmx_cpuid_formatstring(cpuid, str, 1023);
1281 "\nDetecting CPU SIMD instructions.\nPresent hardware specification:\n"
1283 "SIMD instructions most likely to fit this hardware: %s\n"
1284 "SIMD instructions selected at GROMACS compile time: %s\n\n",
1286 gmx_cpuid_simd_string[simd],
1287 gmx_cpuid_simd_string[compiled_simd]);
1294 fprintf(log, "\nBinary not matching hardware - you might be losing performance.\n"
1295 "SIMD instructions most likely to fit this hardware: %s\n"
1296 "SIMD instructions selected at GROMACS compile time: %s\n\n",
1297 gmx_cpuid_simd_string[simd],
1298 gmx_cpuid_simd_string[compiled_simd]);
1300 if (print_to_stderr)
1302 fprintf(stderr, "Compiled SIMD instructions: %s (Gromacs could use %s on this machine, which is better)\n",
1303 gmx_cpuid_simd_string[compiled_simd],
1304 gmx_cpuid_simd_string[simd]);
1311 #ifdef GMX_CPUID_STANDALONE
1312 /* Stand-alone program to enable queries of CPU features from Cmake.
1313 * Note that you need to check inline ASM capabilities before compiling and set
1314 * -DGMX_X86_GCC_INLINE_ASM for the cpuid instruction to work...
1317 main(int argc, char **argv)
1320 enum gmx_cpuid_simd simd;
1326 "Usage:\n\n%s [flags]\n\n"
1327 "Available flags:\n"
1328 "-vendor Print CPU vendor.\n"
1329 "-brand Print CPU brand string.\n"
1330 "-family Print CPU family version.\n"
1331 "-model Print CPU model version.\n"
1332 "-stepping Print CPU stepping version.\n"
1333 "-features Print CPU feature flags.\n"
1334 "-simd Print suggested GROMACS SIMD instructions.\n",
1339 gmx_cpuid_init(&cpuid);
1341 if (!strncmp(argv[1], "-vendor", 3))
1343 printf("%s\n", gmx_cpuid_vendor_string[cpuid->vendor]);
1345 else if (!strncmp(argv[1], "-brand", 3))
1347 printf("%s\n", cpuid->brand);
1349 else if (!strncmp(argv[1], "-family", 3))
1351 printf("%d\n", cpuid->family);
1353 else if (!strncmp(argv[1], "-model", 3))
1355 printf("%d\n", cpuid->model);
1357 else if (!strncmp(argv[1], "-stepping", 3))
1359 printf("%d\n", cpuid->stepping);
1361 else if (!strncmp(argv[1], "-features", 3))
1364 for (i = 0; i < GMX_CPUID_NFEATURES; i++)
1366 if (cpuid->feature[i] == 1)
1372 printf("%s", gmx_cpuid_feature_string[i]);
1377 else if (!strncmp(argv[1], "-simd", 3))
1379 simd = gmx_cpuid_simd_suggest(cpuid);
1380 fprintf(stdout, "%s\n", gmx_cpuid_simd_string[simd]);
1383 gmx_cpuid_done(cpuid);