Add support for Hygon Dhyana processor

This change adds hardware detection and related task assignment
heuristics support for the Hygon Dhyana CPUs.

Chengdu Haiguang IC Design Co., Ltd (Hygon) is a Joint Venture
between AMD and Haiguang Information Technology Co.,Ltd., aims
at providing high performance x86 processor for China server
market. Its first generation processor codename is Dhyana, which
originates from AMD technology and shares most of the architecture
with AMD's family 17h, but with different CPU Vendor ID ("HygonGenuine")
/Family series number (Family 18h).

More details can be found on:
http://lkml.kernel.org/r/5ce86123a7b9dad925ac583d88d2f921040e859b.1538583282.git.puwen@hygon.cn

Change-Id: Ic91b032e69dfc13abad3fbfe6ab5e4f0e57fc7c0

diff --git a/docs/install-guide/index.rst b/docs/install-guide/index.rst
index 76cf1f8ad367c42b47d30b8808544deba7762e25..2b2c78eaf341e5497cc6bbba02f9f0a1f523a193 100644 (file)
--- a/docs/install-guide/index.rst
+++ b/docs/install-guide/index.rst
@@ -541,9 +541,9 @@ lead to performance loss, e.g. on Intel Skylake-X/SP and AMD Zen.
    code will work on the  AMD Bulldozer and Piledriver processors, it is significantly less
    efficient than the ``AVX_128_FMA`` choice above - do not be fooled
    to assume that 256 is better than 128 in this case.
-6. ``AVX2_128`` AMD Zen microarchitecture processors (2017);
+6. ``AVX2_128`` AMD Zen/Zen2 and Hygon Dhyana microarchitecture processors;
    it will enable AVX2 with 3-way fused multiply-add instructions.
-   While the Zen microarchitecture does support 256-bit AVX2 instructions,
+   While these microarchitectures do support 256-bit AVX2 instructions,
    hence ``AVX2_256`` is also supported, 128-bit will generally be faster,
    in particular when the non-bonded tasks run on the CPU -- hence
    the default ``AVX2_128``. With GPU offload however ``AVX2_256``

diff --git a/docs/release-notes/2020/major/portability.rst b/docs/release-notes/2020/major/portability.rst
index 48bba8a2827bb91f28159758a94f1563561813b5..c1c866ca1d59106152a796c12bf791344c30b0c9 100644 (file)
--- a/docs/release-notes/2020/major/portability.rst
+++ b/docs/release-notes/2020/major/portability.rst
@@ -7,3 +7,8 @@ Portability
    Also, please use the syntax :issue:`number` to reference issues on redmine, without the
    a space between the colon and number!
 
+Added support for Hygon Dhyana CPU architecture
+""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
+Support for hardware detection and related heuristics has been implemented
+for the Hygon Dhyana derived from the first-gen AMD Zen which it shares most
+of its architectural details with.

diff --git a/src/gromacs/hardware/cpuinfo.cpp b/src/gromacs/hardware/cpuinfo.cpp
index 644b16d562de223955340ee42aa8451288f9df95..2849a95815a0d4dc5c174d4b6ceb381d073f493f 100644 (file)
--- a/src/gromacs/hardware/cpuinfo.cpp
+++ b/src/gromacs/hardware/cpuinfo.cpp
@@ -1,7 +1,7 @@
 /*
  * This file is part of the GROMACS molecular simulation package.
  *
- * Copyright (c) 2012,2013,2014,2015,2016,2017,2018, by the GROMACS development team, led by
+ * Copyright (c) 2012,2013,2014,2015,2016,2017,2018,2019, by the GROMACS development team, led by
  * Mark Abraham, David van der Spoel, Berk Hess, and Erik Lindahl,
  * and including many others, as listed in the AUTHORS file in the
  * top-level source directory and at http://www.gromacs.org.
@@ -216,11 +216,12 @@ executeX86CpuID(unsigned int     gmx_unused level,
 
 /*! \brief Detect x86 vendors by using the cpuid assembly instructions
  *
- *  If support for the cpuid instruction is present, we check for Intel
- *  or AMD vendors.
+ *  If support for the cpuid instruction is present, we check for Intel,
+ *  AMD or Hygon vendors
  *
- *  \return gmx::CpuInfo::Vendor::Intel, gmx::CpuInfo::Vendor::Amd. If neither
- *          Intel nor Amd can be identified, or if the code fails to execute,
+ *  \return gmx::CpuInfo::Vendor::Intel, gmx::CpuInfo::Vendor::Amd,
+ *          gmx::CpuInfl::Vendor::Hygon, . If neither Intel, Amd  nor
+ *          Hygon can be identified, or if the code fails to execute,
  *          gmx::CpuInfo::Vendor::Unknown is returned.
  */
 CpuInfo::Vendor
@@ -239,6 +240,10 @@ detectX86Vendor()
         {
             v = CpuInfo::Vendor::Amd; // ebx=='htuA', ecx=='DMAc', edx=='itne'
         }
+        else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e)
+        {
+            v = CpuInfo::Vendor::Hygon; // ebx=='ogyH', ecx=='eniu', edx=='neGn'
+        }
     }
     return v;
 }
@@ -618,7 +623,8 @@ detectX86LogicalProcessors()
         }
         else    // haveApic
         {
-            if (detectX86Vendor() == CpuInfo::Vendor::Amd)
+            if (detectX86Vendor() == CpuInfo::Vendor::Amd ||
+                detectX86Vendor() == CpuInfo::Vendor::Hygon)
             {
                 layout = detectAmdApicIdLayout(maxExtLevel);
 
@@ -747,6 +753,8 @@ detectProcCpuInfoVendor(const std::map<std::string, std::string> &cpuInfo)
         { "IBM",          CpuInfo::Vendor::Ibm     },
         { "POWER",        CpuInfo::Vendor::Ibm     },
         { "Oracle",       CpuInfo::Vendor::Oracle  },
+        { "HygonGenuine", CpuInfo::Vendor::Hygon   },
+        { "Hygon",        CpuInfo::Vendor::Hygon   },
     };
 
     // For each label in /proc/cpuinfo, compare the value to the name in the
@@ -966,6 +974,10 @@ CpuInfo CpuInfo::detect()
         {
             result.features_.insert(CpuInfo::Feature::X86_Amd);
         }
+        else if (result.vendor_ == CpuInfo::Vendor::Hygon)
+        {
+            result.features_.insert(CpuInfo::Feature::X86_Hygon);
+        }
         detectX86Features(&result.brandString_, &result.family_, &result.model_,
                           &result.stepping_, &result.features_);
         result.logicalProcessors_ = detectX86LogicalProcessors();
@@ -1035,6 +1047,7 @@ const std::string &CpuInfo::vendorString() const
         { Vendor::Ibm, "IBM"                                 },
         { Vendor::Arm, "ARM"                                 },
         { Vendor::Oracle, "Oracle"                           },
+        { Vendor::Hygon, "Hygon"                             },
     };
 
     return vendorStrings.at(vendor_);
@@ -1095,7 +1108,8 @@ const std::string &CpuInfo::featureString(Feature f)
         { Feature::Ibm_Qpx, "qpx"                            },
         { Feature::Ibm_Vmx, "vmx"                            },
         { Feature::Ibm_Vsx, "vsx"                            },
-        { Feature::Fujitsu_HpcAce, "hpc-ace"                 }
+        { Feature::Fujitsu_HpcAce, "hpc-ace"                 },
+        { Feature::X86_Hygon, "hygon"                        }
     };
     return featureStrings.at(f);
 }

diff --git a/src/gromacs/hardware/cpuinfo.h b/src/gromacs/hardware/cpuinfo.h
index 15c709b61691e03afe7b5990724532e66abe9a38..2f9bb8427e664ca801700d83b716118ed1376933 100644 (file)
--- a/src/gromacs/hardware/cpuinfo.h
+++ b/src/gromacs/hardware/cpuinfo.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the GROMACS molecular simulation package.
  *
- * Copyright (c) 2015,2016,2017,2018, by the GROMACS development team, led by
+ * Copyright (c) 2015,2016,2017,2018,2019, by the GROMACS development team, led by
  * Mark Abraham, David van der Spoel, Berk Hess, and Erik Lindahl,
  * and including many others, as listed in the AUTHORS file in the
  * top-level source directory and at http://www.gromacs.org.
@@ -87,6 +87,7 @@ class CpuInfo
             Ibm,          //!< Only works on Linux (parsed from /proc/cpuinfo)
             Arm,          //!< Only works on Linux (parsed from /proc/cpuinfo)
             Oracle,       //!< Cannot detect anything else yet (no /proc/cpuinfo available)
+            Hygon,        //!< HygonGenuine
         };
 
         /*! \brief List of CPU features
@@ -147,7 +148,8 @@ class CpuInfo
             Ibm_Qpx,         //!< IBM QPX SIMD (BlueGene/Q)
             Ibm_Vmx,         //!< IBM VMX SIMD (Altivec on Power6 and later)
             Ibm_Vsx,         //!< IBM VSX SIMD (Power7 and later)
-            Fujitsu_HpcAce   //!< Fujitsu Sparc64 HPC-ACE
+            Fujitsu_HpcAce,  //!< Fujitsu Sparc64 HPC-ACE
+            X86_Hygon        //!< This is a Hygon x86 processor
         };
 
         /*! \libinternal \brief Entry with basic information for a single logical processor */

diff --git a/src/gromacs/hardware/detecthardware.cpp b/src/gromacs/hardware/detecthardware.cpp
index ff683eb49ba7c4c42ce4bf506a86ad6fb91edfe0..a28bde8d4b2bba8662bba2ff3cd98a845eaae5ac 100644 (file)
--- a/src/gromacs/hardware/detecthardware.cpp
+++ b/src/gromacs/hardware/detecthardware.cpp
@@ -187,9 +187,12 @@ static void gmx_collect_hardware_mpi(const gmx::CpuInfo             &cpuInfo,
                                      const PhysicalNodeCommunicator &physicalNodeComm)
 {
     const int  ncore        = hwinfo_g->hardwareTopology->numberOfCores();
-    /* Zen has family=23, for now we treat future AMD CPUs like Zen */
-    const bool cpuIsAmdZen  = (cpuInfo.vendor() == CpuInfo::Vendor::Amd &&
-                               cpuInfo.family() >= 23);
+    /* Zen has family=23, for now we treat future AMD CPUs like Zen
+     * and Hygon Dhyana like Zen */
+    const bool cpuIsAmdZen  = ((cpuInfo.vendor() == CpuInfo::Vendor::Amd &&
+                                cpuInfo.family() >= 23) ||
+                               cpuInfo.vendor() == CpuInfo::Vendor::Hygon);
+    ;
 
 #if GMX_LIB_MPI
     int       nhwthread, ngpu, i;

diff --git a/src/gromacs/hardware/hw_info.h b/src/gromacs/hardware/hw_info.h
index 320fbf3433d7435ad8d0fc9743f783624031b83a..b77d707b9b6629c301b4e0d0a02ca971f5d0b6fd 100644 (file)
--- a/src/gromacs/hardware/hw_info.h
+++ b/src/gromacs/hardware/hw_info.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the GROMACS molecular simulation package.
  *
- * Copyright (c) 2012,2013,2014,2015,2016,2017, by the GROMACS development team, led by
+ * Copyright (c) 2012,2013,2014,2015,2016,2017,2019, by the GROMACS development team, led by
  * Mark Abraham, David van der Spoel, Berk Hess, and Erik Lindahl,
  * and including many others, as listed in the AUTHORS file in the
  * top-level source directory and at http://www.gromacs.org.
@@ -79,7 +79,7 @@ struct gmx_hw_info_t
     int                 simd_suggest_max;    /* Highest SIMD instruction set supported by at least one rank */
 
     gmx_bool            bIdenticalGPUs;      /* TRUE if all ranks have the same type(s) and order of GPUs */
-    bool                haveAmdZenCpu;       /* TRUE when at least one CPU in any of the nodes is AMD Zen */
+    bool                haveAmdZenCpu;       /* TRUE when at least one CPU in any of the nodes is AMD Zen arch */
 };
 
 

diff --git a/src/gromacs/simd/support.cpp b/src/gromacs/simd/support.cpp
index d7b5839251d9ad3957d283aee2513ef9f92cdc17..8b334bb0b0fdc094696eef6726c028f53f983ec1 100644 (file)
--- a/src/gromacs/simd/support.cpp
+++ b/src/gromacs/simd/support.cpp
@@ -1,7 +1,7 @@
 /*
  * This file is part of the GROMACS molecular simulation package.
  *
- * Copyright (c) 2015,2016,2017,2018, by the GROMACS development team, led by
+ * Copyright (c) 2015,2016,2017,2018,2019, by the GROMACS development team, led by
  * Mark Abraham, David van der Spoel, Berk Hess, and Erik Lindahl,
  * and including many others, as listed in the AUTHORS file in the
  * top-level source directory and at http://www.gromacs.org.
@@ -127,6 +127,7 @@ simdSuggested(const CpuInfo &c)
                 }
                 break;
             case CpuInfo::Vendor::Amd:
+            case CpuInfo::Vendor::Hygon:
                 if (c.feature(CpuInfo::Feature::X86_Avx2))
                 {
                     // AMD Ryzen supports 256-bit AVX2, but performs better with 128-bit

diff --git a/src/gromacs/taskassignment/resourcedivision.cpp b/src/gromacs/taskassignment/resourcedivision.cpp
index 9c83a9b9b3c9b62b9c9c8ca952347f6c56ad67f0..88f03fabefab447ec2c02ad66d98f730f219fbc1 100644 (file)
--- a/src/gromacs/taskassignment/resourcedivision.cpp
+++ b/src/gromacs/taskassignment/resourcedivision.cpp
@@ -156,9 +156,10 @@ static int nthreads_omp_faster(const gmx::CpuInfo &cpuInfo, gmx_bool bUseGPU)
         // Intel Nehalem
         nth = nthreads_omp_faster_Nehalem;
     }
-    else if (cpuInfo.vendor() == gmx::CpuInfo::Vendor::Amd && cpuInfo.family() >= 23)
+    else if ((cpuInfo.vendor() == gmx::CpuInfo::Vendor::Amd && cpuInfo.family() >= 23) ||
+             cpuInfo.vendor() == gmx::CpuInfo::Vendor::Hygon)
     {
-        // AMD Ryzen
+        // AMD Ryzen || Hygon Dhyana
         nth = nthreads_omp_faster_AMD_Ryzen;
     }
     else