{
cudaError_t stat;
char strbuf[STRLEN];
- int flag = cudaHostAllocDefault || cudaHostAllocWriteCombined;
+ int flag = cudaHostAllocDefault | cudaHostAllocWriteCombined;
if (nbytes == 0)
{
const gmx_bool bGPUBinary = FALSE;
#endif
+/* Names of the GPU detection/check results (see e_gpu_detect_res_t in hw_info.h). */
+const char * const gpu_detect_res_str[egpuNR] =
+{
+ "compatible", "inexistent", "incompatible", "insane"
+};
+
static const char * invalid_gpuid_hint =
"A delimiter-free sequence of valid numeric IDs of available GPUs is expected.";
* incompatible driver/runtime. */
typedef enum
{
- egpuCompatible = 0, egpuNonexistent, egpuIncompatible, egpuInsane
+ egpuCompatible = 0, egpuNonexistent, egpuIncompatible, egpuInsane, egpuNR
} e_gpu_detect_res_t;
-/* Textual names of the GPU detection/check results (see e_gpu_detect_res_t). */
-static const char * const gpu_detect_res_str[] =
-{
- "compatible", "inexistent", "incompatible", "insane"
-};
+/* Names of the GPU detection/check results */
+extern const char * const gpu_detect_res_str[egpuNR];
/* GPU device information -- for now with only CUDA devices
* The gmx_hardware_detect module initializes it. */
* Bit i*CJ_SIZE + j tells if atom i and j interact.
*/
/* All interaction mask is the same for all kernels */
-static const unsigned int NBNXN_INTERACTION_MASK_ALL = 0xffffffffU;
+#define NBNXN_INTERACTION_MASK_ALL 0xffffffffU
/* 4x4 kernel diagonal mask */
-static const unsigned int NBNXN_INTERACTION_MASK_DIAG = 0x08ceU;
+#define NBNXN_INTERACTION_MASK_DIAG 0x08ceU
/* 4x2 kernel diagonal masks */
-static const unsigned int NBNXN_INTERACTION_MASK_DIAG_J2_0 = 0x0002U;
-static const unsigned int NBNXN_INTERACTION_MASK_DIAG_J2_1 = 0x002fU;
+#define NBNXN_INTERACTION_MASK_DIAG_J2_0 0x0002U
+#define NBNXN_INTERACTION_MASK_DIAG_J2_1 0x002fU
/* 4x8 kernel diagonal masks */
-static const unsigned int NBNXN_INTERACTION_MASK_DIAG_J8_0 = 0xf0f8fcfeU;
-static const unsigned int NBNXN_INTERACTION_MASK_DIAG_J8_1 = 0x0080c0e0U;
+#define NBNXN_INTERACTION_MASK_DIAG_J8_0 0xf0f8fcfeU
+#define NBNXN_INTERACTION_MASK_DIAG_J8_1 0x0080c0e0U
#ifdef __cplusplus
#endif
for (jm = 0; jm < NBNXN_GPU_JGROUP_SIZE; jm++)
{
- if (imask & (supercl_interaction_mask << (jm * NCL_PER_SUPERCL)))
+ /* ((1U << NCL_PER_SUPERCL) - 1U) is the i-cluster interaction
+ * mask for a super-cluster with all NCL_PER_SUPERCL bits set.
+ */
+ if (imask & (((1U << NCL_PER_SUPERCL) - 1U) << (jm * NCL_PER_SUPERCL)))
{
mask_ji = (1U << (jm * NCL_PER_SUPERCL));
#define ONE_TWELVETH_F 0.08333333f
-/*! i-cluster interaction mask for a super-cluster with all NCL_PER_SUPERCL bits set */
-const unsigned supercl_interaction_mask = ((1U << NCL_PER_SUPERCL) - 1U);
-
/*! Apply force switch, force + energy version. */
static inline __device__
void calculate_force_switch_F(const cu_nbparam_t nbparam,