docs: add ARM+SVE support to the release notes and SIMD support documentation

diff --git a/docs/install-guide/index.rst b/docs/install-guide/index.rst
index fafbb096ca38c9a719ada00e202fba79309d5500..438802188eb78613ac41e85463fb4d712cd0bb6c 100644 (file)
--- a/docs/install-guide/index.rst
+++ b/docs/install-guide/index.rst
@@ -575,6 +575,10 @@ lead to performance loss, e.g. on Intel Skylake-X/SP and AMD Zen.
 12. ``IBM_VSX`` Power7, Power8, Power9 and later have this.
 13. ``ARM_NEON`` 32-bit ARMv7 with NEON support.
 14. ``ARM_NEON_ASIMD`` 64-bit ARMv8 and later.
+15. ``ARM_SVE`` 64-bit ARMv8 and later with the Scalable Vector Extensions (SVE).
+    The SVE vector length is fixed at CMake configure time. The default vector
+    length is 512 bits, and this can be changed via the ``GMX_SIMD_ARM_SVE_LENGTH``
+    CMake variable.
 
 The CMake configure system will check that the compiler you have
 chosen can target the architecture you have chosen. mdrun will check

diff --git a/docs/release-notes/2021/major/portability.rst b/docs/release-notes/2021/major/portability.rst
index a9e483e0ca54966b4325c04931ab6ecf12c5f3e8..75e2449a7973556eb4f891baad8860df4cb23310 100644 (file)
--- a/docs/release-notes/2021/major/portability.rst
+++ b/docs/release-notes/2021/major/portability.rst
@@ -51,3 +51,16 @@ instruction for lower latency timing. Very old machines might need to
 configure with ``GMX_USE_RDTSCP=off``. Non-x86 platforms are
 unaffected, except that they will no longer report that RDTSCP is
 disabled (because that is self-evident).
+
+armv8+sve support (ARM_SVE)
+"""""""""""""""""""""""""""
+Support for ARM Scalable Vector Extensions (SVE) has been added.
+|Gromacs| supports SVE vector length fixed at CMake configure time
+(typically via the -msve-vector-bits=<len> compiler option),
+which is at the time of the release supported in GNU GCC 10 and later,
+and will supported soon by LLVM 12 and compilers based on this.
+The default vector length is 512 bits, and that can be changed at
+CMake configure time with ``GMX_SIMD_ARM_SVE_LENGTH=<bits>`` option.
+Supported values are 128, 256, 512 and 1024. Note that the nonbonded
+kernels have not been optimized for ARM_SVE as of yet.
+ARM_SVE support is contributed by the Research Organization for Science Information and Technology (RIST)

diff --git a/docs/user-guide/mdrun-performance.rst b/docs/user-guide/mdrun-performance.rst
index 1309ac080633456099654290bbc5fd56512ff121..09f245547ae3c3752339756fff69c629626c8b37 100644 (file)
--- a/docs/user-guide/mdrun-performance.rst
+++ b/docs/user-guide/mdrun-performance.rst
@@ -213,6 +213,18 @@ of the better clock frequency available. Consider building :ref:`mdrun <gmx mdru
 configured with ``GMX_SIMD=AVX2_256`` instead of ``GMX_SIMD=AVX512`` for better
 performance in GPU accelerated or highly parallel MPI runs.
 
+Some latest ARM based CPU, such as A64fx, support the Scalable Vector Extensions (SVE).
+Though SVE can be used to generate fairly efficient Vector Length Agnostic (VLA) code,
+VLA is not a fit for GROMACS (that currently assumes the SIMD vector length is known at
+CMake time). Consequently, the SVE vector length must be fixed at CMake time. The default
+value is 512 bits, and this can be changed with ``GMX_SIMD_ARM_SVE_LENGTH=<len>``.
+The supported vector length are 128, 256, 512 and 1024. Since GROMACS optimized non-bonded kernels
+only support up to 16 floating point numbers per SIMD vector, 1024 bits vector length is only
+valid in double precision (e.g. ``-DGMX_DOUBLE=on``).
+Note that even if `mdrun` does check the SIMD vector length at runtime, running with a different
+vector length than the one used at CMake time is undefined behavior, and `mdrun` might crash before reaching
+the check (that would abort with a user-friendly error message).
+
 Process(-or) level parallelization via OpenMP
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^