The gcc code has been tested on actual ARM64
hardware, but the MSVC one is only implemented
from the MSVC manual.
Change-Id: I13aac4d65345c684b6ddc5812ca9c3fcbe27b81a
typedef unsigned long long
gmx_cycles_t;
typedef unsigned long long
gmx_cycles_t;
+#elif ((defined __aarch64__) && (defined(__GNUC__) || defined(__INTEL_COMPILER) || defined(__PATHSCALE__) || defined(__PGIC__)))
+/* 64-bit ARM cycle counters with GCC inline assembly */
+typedef unsigned long long
+ gmx_cycles_t;
+
#elif defined(_MSC_VER)
#include <windows.h>
typedef __int64
#elif defined(_MSC_VER)
#include <windows.h>
typedef __int64
/* x86 or x86-64 with GCC inline assembly - pentium TSC register */
return 1;
}
/* x86 or x86-64 with GCC inline assembly - pentium TSC register */
return 1;
}
+#elif ((defined __aarch64__) && (defined(__GNUC__) || defined(__INTEL_COMPILER) || defined(__PATHSCALE__) || defined(__PGIC__)))
+static __inline int gmx_cycles_have_counter(void)
+{
+ /* 64-bit ARM cycle counters with GCC inline assembly */
+ return 1;
+}
#elif (defined(_MSC_VER))
static __inline int gmx_cycles_have_counter(void)
{
#elif (defined(_MSC_VER))
static __inline int gmx_cycles_have_counter(void)
{
+#elif ((defined __aarch64__) && (defined(__GNUC__) || defined(__INTEL_COMPILER) || defined(__PATHSCALE__) || defined(__PGIC__)))
+static __inline__ gmx_cycles_t gmx_cycles_read(void)
+{
+ /* 64-bit ARM cycle counters with GCC inline assembly */
+ gmx_cycles_t cycle;
+ __asm__ __volatile__("mrs %0, cntvct_el0" : "=r" (cycle) );
+
+ return cycle;
+}
+
#elif defined(_MSC_VER)
static __inline gmx_cycles_t gmx_cycles_read(void)
{
#elif defined(_MSC_VER)
static __inline gmx_cycles_t gmx_cycles_read(void)
{
+#ifdef _M_ARM
+ /* Windows on 64-bit ARM */
+ return __rdpmccntr64();
+#else
+ /* x86 */
+# ifdef HAVE_RDTSCP
unsigned int ui;
return __rdtscp(&ui);
unsigned int ui;
return __rdtscp(&ui);
#endif
}
#elif (defined(__hpux) || defined(__HP_cc)) && defined(__ia64)
#endif
}
#elif (defined(__hpux) || defined(__HP_cc)) && defined(__ia64)