Merge branch release-2019 into master

[alexxy/gromacs.git] / src / gromacs / simd / support.cpp

diff --git a/src/gromacs/simd/support.cpp b/src/gromacs/simd/support.cpp
index 8b334bb0b0fdc094696eef6726c028f53f983ec1..220b782cdb6cfa3c53563015371689313f068873 100644 (file)
--- a/src/gromacs/simd/support.cpp
+++ b/src/gromacs/simd/support.cpp
@@ -90,6 +90,30 @@ simdString(SimdType s)
     return name.at(s);
 }
 
+namespace
+{
+
+
+//! Helper to detect correct AMD Zen architecture.
+bool
+cpuIsAmdZen1(const CpuInfo &cpuInfo)
+{
+    // Both Zen/Zen+/Zen2 have family==23
+    // Model numbers for Zen:
+    // 1)  Naples, Whitehaven, Summit ridge, and Snowy Owl
+    // 17) Raven ridge
+    // Model numbers for Zen+:
+    // 8)  Pinnacle Ridge
+    // 24) Picasso
+    return (cpuInfo.vendor() == gmx::CpuInfo::Vendor::Amd &&
+            cpuInfo.family() == 23 &&
+            (cpuInfo.model() == 1 || cpuInfo.model() == 17 ||
+             cpuInfo.model() == 8 || cpuInfo.model() == 24) );
+}
+
+}   // namespace
+
+
 SimdType
 simdSuggested(const CpuInfo &c)
 {
@@ -130,10 +154,12 @@ simdSuggested(const CpuInfo &c)
             case CpuInfo::Vendor::Hygon:
                 if (c.feature(CpuInfo::Feature::X86_Avx2))
                 {
-                    // AMD Ryzen supports 256-bit AVX2, but performs better with 128-bit
+                    // AMD Zen supports 256-bit AVX2, but Zen1 performs better with 128-bit
                     // since it can execute two independent such instructions per cycle,
                     // and wider SIMD has slightly lower efficiency in GROMACS.
-                    suggested = SimdType::X86_Avx2_128;
+                    // However... Zen2 supports full-width execution of 256-bit AVX2,
+                    // so we only want to apply this hack to Zen/Zen+.
+                    suggested = cpuIsAmdZen1(c) ? SimdType::X86_Avx2_128 : SimdType::X86_Avx2;
                 }
                 else if (c.feature(CpuInfo::Feature::X86_Avx))
                 {