GMX_CPUID_VENDOR_AMD,
GMX_CPUID_VENDOR_FUJITSU,
GMX_CPUID_VENDOR_IBM,
+ GMX_CPUID_VENDOR_ARM,
GMX_CPUID_NVENDORS
};
GMX_CPUID_FEATURE_X86_APIC, /* APIC support */
GMX_CPUID_FEATURE_X86_AVX, /* Advanced vector extensions */
GMX_CPUID_FEATURE_X86_AVX2, /* AVX2 including gather support (not used yet) */
+ GMX_CPUID_FEATURE_X86_AVX_512F, /* Foundation AVX-512 instructions */
+ GMX_CPUID_FEATURE_X86_AVX_512PF, /* Extended gather/scatter for AVX-512 */
+ GMX_CPUID_FEATURE_X86_AVX_512ER, /* Extended-range 1/x and /1sqrt(x) for AVX-512 */
+ GMX_CPUID_FEATURE_X86_AVX_512CD, /* Memory conflict-detection for AVX-512 */
GMX_CPUID_FEATURE_X86_CLFSH, /* Supports CLFLUSH instruction */
GMX_CPUID_FEATURE_X86_CMOV, /* Conditional move insn support */
GMX_CPUID_FEATURE_X86_CX8, /* Supports CMPXCHG8B (8-byte compare-exchange) */
GMX_CPUID_FEATURE_X86_TDT, /* TSC deadline timer */
GMX_CPUID_FEATURE_X86_X2APIC, /* Extended xAPIC Support */
GMX_CPUID_FEATURE_X86_XOP, /* AMD extended instructions, only AMD for now */
+ GMX_CPUID_FEATURE_ARM_NEON, /* 32-bit ARM NEON */
+ GMX_CPUID_FEATURE_ARM_NEON_ASIMD, /* 64-bit ARM AArch64 Advanced SIMD */
+ GMX_CPUID_FEATURE_IBM_QPX, /* IBM QPX SIMD (BlueGene/Q and later) */
+ GMX_CPUID_FEATURE_IBM_VMX, /* IBM VMX SIMD (Altivec on Power6 and later) */
+ GMX_CPUID_FEATURE_IBM_VSX, /* IBM VSX SIMD (Power7 and later) */
GMX_CPUID_NFEATURES
};
GMX_CPUID_SIMD_X86_AVX_128_FMA,
GMX_CPUID_SIMD_X86_AVX_256,
GMX_CPUID_SIMD_X86_AVX2_256,
+ GMX_CPUID_SIMD_X86_AVX_512F,
+ GMX_CPUID_SIMD_X86_AVX_512ER,
GMX_CPUID_SIMD_SPARC64_HPC_ACE,
GMX_CPUID_SIMD_IBM_QPX,
+ GMX_CPUID_SIMD_IBM_VMX,
+ GMX_CPUID_SIMD_IBM_VSX,
+ GMX_CPUID_SIMD_ARM_NEON,
+ GMX_CPUID_SIMD_ARM_NEON_ASIMD,
GMX_CPUID_NSIMD
};