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35 #ifndef _nbnxn_kernel_simd_utils_x86_mic_h_
36 #define _nbnxn_kernel_simd_utils_x86_mic_h_
38 typedef gmx_simd_int32_t gmx_exclfilter;
39 static const int filter_stride = GMX_SIMD_INT32_WIDTH/GMX_SIMD_REAL_WIDTH;
41 #define PERM_LOW2HIGH _MM_PERM_BABA
42 #define PERM_HIGH2LOW _MM_PERM_DCDC
44 #define mask_loh _mm512_int2mask(0x00FF) /* would be better a constant - but can't initialize with a function call. */
45 #define mask_hih _mm512_int2mask(0xFF00)
47 /* float/double SIMD register type */
48 typedef __m512 gmx_mm_pr4;
50 static gmx_inline gmx_mm_pr4
51 gmx_load_pr4(const real *r)
53 return _mm512_loadunpacklo_ps(_mm512_undefined_ps(), r);
56 static gmx_inline void
57 gmx_store_pr4(real *dest, gmx_mm_pr4 src)
59 _mm512_mask_packstorelo_ps(dest, _mm512_int2mask(0xF), src);
62 static gmx_inline gmx_mm_pr4
63 gmx_add_pr4(gmx_mm_pr4 a, gmx_mm_pr4 b)
65 return _mm512_add_ps(a, b);
68 /* Half-width SIMD real type */
69 typedef __m512 gmx_mm_hpr; /* high half is ignored */
71 /* Half-width SIMD operations */
73 /* Load reals at half-width aligned pointer b into half-width SIMD register a */
74 static gmx_inline void
75 gmx_load_hpr(gmx_mm_hpr *a, const real *b)
77 *a = _mm512_loadunpacklo_ps(_mm512_undefined_ps(), b);
80 /* Set all entries in half-width SIMD register *a to b */
81 static gmx_inline void
82 gmx_set1_hpr(gmx_mm_hpr *a, real b)
84 *a = _mm512_set1_ps(b);
87 /* Load one real at b and one real at b+1 into halves of a, respectively */
88 static gmx_inline void
89 gmx_load1p1_pr(gmx_mm_ps *a, const real *b)
92 *a = _mm512_mask_extload_ps(_mm512_extload_ps(b, _MM_UPCONV_PS_NONE, _MM_BROADCAST_1X16, _MM_HINT_NONE), mask_hih,
93 b+1, _MM_UPCONV_PS_NONE, _MM_BROADCAST_1X16, _MM_HINT_NONE);
96 /* Load reals at half-width aligned pointer b into two halves of a */
97 static gmx_inline void
98 gmx_loaddh_pr(gmx_mm_ps *a, const real *b)
100 *a = _mm512_permute4f128_ps(_mm512_loadunpacklo_ps(_mm512_undefined_ps(), b), PERM_LOW2HIGH);
103 /* Store half-width SIMD register b into half width aligned memory a */
104 static gmx_inline void
105 gmx_store_hpr(real *a, gmx_mm_hpr b)
107 _mm512_mask_packstorelo_ps(a, mask_loh, b);
110 #define gmx_add_hpr _mm512_add_ps
111 #define gmx_sub_hpr _mm512_sub_ps
113 /* Sum over 4 half SIMD registers */
114 static gmx_inline gmx_mm_hpr
115 gmx_sum4_hpr(gmx_mm_ps a, gmx_mm_ps b)
117 a = _mm512_add_ps(a, b);
118 b = _mm512_permute4f128_ps(a, PERM_HIGH2LOW);
119 return _mm512_add_ps(a, b);
122 /* Sum the elements of halfs of each input register and store sums in out */
123 static gmx_inline gmx_mm_pr4
124 gmx_mm_transpose_sum4h_pr(gmx_mm_ps a, gmx_mm_ps b)
126 return _mm512_setr4_ps(_mm512_mask_reduce_add_ps(mask_loh, a),
127 _mm512_mask_reduce_add_ps(mask_hih, a),
128 _mm512_mask_reduce_add_ps(mask_loh, b),
129 _mm512_mask_reduce_add_ps(mask_hih, b));
132 static gmx_inline void
133 gmx_pr_to_2hpr(gmx_mm_ps a, gmx_mm_hpr *b, gmx_mm_hpr *c)
136 *c = _mm512_permute4f128_ps(a, PERM_HIGH2LOW);
139 static gmx_inline void
140 gmx_2hpr_to_pr(gmx_mm_hpr a, gmx_mm_hpr b, gmx_mm_ps *c)
142 *c = _mm512_mask_permute4f128_ps(a, mask_hih, b, PERM_LOW2HIGH);
145 /* recombine the 2 high half into c */
146 static gmx_inline void
147 gmx_2hpr_high_to_pr(gmx_mm_hpr a, gmx_mm_hpr b, gmx_mm_ps *c)
149 *c = _mm512_mask_permute4f128_ps(b, mask_loh, a, PERM_HIGH2LOW);
152 static gmx_inline void
153 gmx_2hepi_to_epi(gmx_simd_int32_t a, gmx_simd_int32_t b, gmx_simd_int32_t *c)
155 *c = _mm512_mask_permute4f128_epi32(a, mask_hih, b, PERM_LOW2HIGH);
158 /* recombine the 2 high half into c */
159 static gmx_inline void
160 gmx_2hepi_high_to_epi(gmx_simd_int32_t a, gmx_simd_int32_t b, gmx_simd_int32_t *c)
162 *c = _mm512_mask_permute4f128_epi32(b, mask_loh, a, PERM_HIGH2LOW);
165 /* Align a stack-based thread-local working array. work-array (currently) not used by load_table_f*/
166 static gmx_inline int *
167 prepare_table_load_buffer(const int *array)
172 /* Using TAB_FDV0 is slower (for non-analytical PME). For the _mm512_i32gather_ps it helps
173 to have the 16 elements in fewer cache lines. This is why it is faster to do F&D toghether
174 and low/high half after each other, then simply doing a gather for tab_coul_F and tab_coul_F+1.
175 The ording of the 16 elements doesn't matter, so it doesn't help to get FD sorted as odd/even
178 static gmx_inline void
179 load_table_f(const real *tab_coul_F, gmx_simd_int32_t ti_S, int *ti,
180 gmx_mm_ps *ctab0_S, gmx_mm_ps *ctab1_S)
183 __m512i ti1 = _mm512_add_epi32(ti_S, _mm512_set1_epi32(1)); /* incr by 1 for tab1 */
184 gmx_2hepi_to_epi(ti_S, ti1, &idx);
185 __m512 tmp1 = _mm512_i32gather_ps(idx, tab_coul_F, sizeof(float));
186 gmx_2hepi_high_to_epi(ti_S, ti1, &idx);
187 __m512 tmp2 = _mm512_i32gather_ps(idx, tab_coul_F, sizeof(float));
189 gmx_2hpr_to_pr(tmp1, tmp2, ctab0_S);
190 gmx_2hpr_high_to_pr(tmp1, tmp2, ctab1_S);
191 *ctab1_S = gmx_simd_sub_r(*ctab1_S, *ctab0_S);
194 static gmx_inline void
195 load_table_f_v(const real *tab_coul_F, const real *tab_coul_V,
196 gmx_simd_int32_t ti_S, int *ti,
197 gmx_mm_ps *ctab0_S, gmx_mm_ps *ctab1_S,
200 load_table_f(tab_coul_F, ti_S, ti, ctab0_S, ctab1_S);
201 *ctabv_S = _mm512_i32gather_ps(ti_S, tab_coul_V, sizeof(float));
204 static gmx_inline gmx_mm_pr4
205 gmx_mm_transpose_sum4_pr(gmx_mm_ps in0, gmx_mm_ps in1,
206 gmx_mm_ps in2, gmx_mm_ps in3)
208 return _mm512_setr4_ps(_mm512_reduce_add_ps(in0),
209 _mm512_reduce_add_ps(in1),
210 _mm512_reduce_add_ps(in2),
211 _mm512_reduce_add_ps(in3));
214 static gmx_inline void
215 load_lj_pair_params2(const real *nbfp0, const real *nbfp1,
216 const int *type, int aj,
217 gmx_mm_ps *c6_S, gmx_mm_ps *c12_S)
219 __m512i idx0, idx1, idx;
221 /* load all 8 unaligned requires 2 load. */
222 idx0 = _mm512_loadunpacklo_epi32(_mm512_undefined_epi32(), type+aj);
223 idx0 = _mm512_loadunpackhi_epi32(idx0, type+aj+16);
225 idx0 = _mm512_mullo_epi32(idx0, _mm512_set1_epi32(nbfp_stride));
226 idx1 = _mm512_add_epi32(idx0, _mm512_set1_epi32(1)); /* incr by 1 for c12 */
228 gmx_2hepi_to_epi(idx0, idx1, &idx);
229 __m512 tmp1 = _mm512_i32gather_ps(idx, nbfp0, sizeof(float));
230 __m512 tmp2 = _mm512_i32gather_ps(idx, nbfp1, sizeof(float));
232 gmx_2hpr_to_pr(tmp1, tmp2, c6_S);
233 gmx_2hpr_high_to_pr(tmp1, tmp2, c12_S);
236 #define HAVE_GMX_SUM_SIMD
237 static gmx_inline real
238 gmx_sum_simd(gmx_simd_real_t x, real* b)
240 return _mm512_reduce_add_ps(x);
242 static gmx_inline real
243 gmx_sum_simd4(gmx_simd_real_t x, real* b)
245 return _mm512_mask_reduce_add_ps(_mm512_int2mask(0xF), x);
248 /* Code for handling loading exclusions and converting them into
250 #define gmx_load1_exclfilter _mm512_set1_epi32
251 #define gmx_load_exclusion_filter _mm512_load_epi32
252 #define gmx_checkbitmask_pb _mm512_test_epi32_mask
254 #endif /* _nbnxn_kernel_simd_utils_ref_h_ */