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35 #ifndef _nbnxn_kernel_simd_utils_x86_256s_h_
36 #define _nbnxn_kernel_simd_utils_x86_256s_h_
38 /* This files contains all functions/macros for the SIMD kernels
39 * which have explicit dependencies on the j-cluster size and/or SIMD-width.
40 * The functionality which depends on the j-cluster size is:
43 * energy group pair energy storage
47 #ifdef GMX_NBNXN_SIMD_2XNN
48 /* Half-width operations are required for the 2xnn kernels */
50 /* Half-width SIMD real type */
51 #define gmx_mm_hpr __m128
53 /* Half-width SIMD operations */
54 /* Load reals at half-width aligned pointer b into half-width SIMD register a */
55 #define gmx_load_hpr(a, b) *(a) = _mm_load_ps(b)
56 /* Set all entries in half-width SIMD register *a to b */
57 #define gmx_set1_hpr(a, b) *(a) = _mm_set1_ps(b)
58 /* Load one real at b and one real at b+1 into halves of a, respectively */
59 #define gmx_load1p1_pr(a, b) *(a) = _mm256_insertf128_ps(_mm256_castps128_ps256(_mm_load1_ps(b)), _mm_load1_ps(b+1), 0x1)
60 /* To half-width SIMD register b into half width aligned memory a */
61 #define gmx_store_hpr(a, b) _mm_store_ps(a, b)
62 #define gmx_add_hpr _mm_add_ps
63 #define gmx_sub_hpr _mm_sub_ps
65 /* Sum over 4 half SIMD registers */
66 static __m128 gmx_simdcall gmx_sum4_hpr(__m256 x, __m256 y)
70 sum = _mm256_add_ps(x, y);
71 return _mm_add_ps(_mm256_castps256_ps128(sum), _mm256_extractf128_ps(sum, 0x1));
74 /* Load reals at half-width aligned pointer b into two halves of a */
75 static gmx_inline void
76 gmx_loaddh_pr(gmx_simd_real_t *a, const real *b)
80 *a = _mm256_insertf128_ps(_mm256_castps128_ps256(tmp), tmp, 0x1);
83 static gmx_inline void gmx_simdcall
84 gmx_pr_to_2hpr(gmx_simd_real_t a, gmx_mm_hpr *b, gmx_mm_hpr *c)
86 *b = _mm256_extractf128_ps(a, 0);
87 *c = _mm256_extractf128_ps(a, 1);
90 /* Store half width SIMD registers a and b in full width register *c */
91 static gmx_inline void gmx_simdcall
92 gmx_2hpr_to_pr(gmx_mm_hpr a, gmx_mm_hpr b, gmx_simd_real_t *c)
94 *c = _mm256_insertf128_ps(_mm256_castps128_ps256(a), b, 0x1);
97 #endif /* GMX_NBNXN_SIMD_2XNN */
99 /* Collect element 0 and 1 of the 4 inputs to out0 and out1, respectively */
100 static gmx_inline void gmx_simdcall
101 gmx_shuffle_4_ps_fil01_to_2_ps(__m128 in0, __m128 in1, __m128 in2, __m128 in3,
102 __m128 *out0, __m128 *out1)
106 _c01 = _mm_movelh_ps(in0, in1);
107 _c23 = _mm_movelh_ps(in2, in3);
108 *out0 = _mm_shuffle_ps(_c01, _c23, _MM_SHUFFLE(2, 0, 2, 0));
109 *out1 = _mm_shuffle_ps(_c01, _c23, _MM_SHUFFLE(3, 1, 3, 1));
112 /* Collect element 2 of the 4 inputs to out */
113 static gmx_inline __m128 gmx_simdcall
114 gmx_shuffle_4_ps_fil2_to_1_ps(__m128 in0, __m128 in1, __m128 in2, __m128 in3)
118 _c01 = _mm_shuffle_ps(in0, in1, _MM_SHUFFLE(3, 2, 3, 2));
119 _c23 = _mm_shuffle_ps(in2, in3, _MM_SHUFFLE(3, 2, 3, 2));
121 return _mm_shuffle_ps(_c01, _c23, _MM_SHUFFLE(2, 0, 2, 0));
124 /* Sum the elements within each input register and return the sums */
125 static gmx_inline __m128 gmx_simdcall
126 gmx_mm_transpose_sum4_pr(__m256 in0, __m256 in1,
127 __m256 in2, __m256 in3)
129 in0 = _mm256_hadd_ps(in0, in1);
130 in2 = _mm256_hadd_ps(in2, in3);
131 in1 = _mm256_hadd_ps(in0, in2);
133 return _mm_add_ps(_mm256_castps256_ps128(in1),
134 _mm256_extractf128_ps(in1, 1));
137 /* Sum the elements of halfs of each input register and return the sums */
138 static gmx_inline __m128 gmx_simdcall
139 gmx_mm_transpose_sum4h_pr(__m256 in0, __m256 in2)
141 in0 = _mm256_hadd_ps(in0, _mm256_setzero_ps());
142 in2 = _mm256_hadd_ps(in2, _mm256_setzero_ps());
143 in0 = _mm256_hadd_ps(in0, in2);
144 in2 = _mm256_permute_ps(in0, _MM_SHUFFLE(2, 3, 0, 1));
146 return _mm_add_ps(_mm256_castps256_ps128(in0), _mm256_extractf128_ps(in2, 1));
149 /* Put two 128-bit 4-float registers into one 256-bit 8-float register */
150 static gmx_inline __m256 gmx_simdcall
151 gmx_2_mm_to_m256(__m128 in0, __m128 in1)
153 return _mm256_insertf128_ps(_mm256_castps128_ps256(in0), in1, 1);
157 static gmx_inline void
158 load_lj_pair_params(const real *nbfp, const int *type, int aj,
159 __m256 *c6_S, __m256 *c12_S)
161 __m128 clj_S[UNROLLJ], c6t_S[2], c12t_S[2];
164 for (p = 0; p < UNROLLJ; p++)
166 /* Here we load 4 aligned floats, but we need just 2 */
167 clj_S[p] = _mm_load_ps(nbfp+type[aj+p]*nbfp_stride);
169 gmx_shuffle_4_ps_fil01_to_2_ps(clj_S[0], clj_S[1], clj_S[2], clj_S[3],
170 &c6t_S[0], &c12t_S[0]);
171 gmx_shuffle_4_ps_fil01_to_2_ps(clj_S[4], clj_S[5], clj_S[6], clj_S[7],
172 &c6t_S[1], &c12t_S[1]);
174 *c6_S = gmx_2_mm_to_m256(c6t_S[0], c6t_S[1]);
175 *c12_S = gmx_2_mm_to_m256(c12t_S[0], c12t_S[1]);
180 static gmx_inline void
181 load_lj_pair_params2(const real *nbfp0, const real *nbfp1,
182 const int *type, int aj,
183 __m256 *c6_S, __m256 *c12_S)
185 __m128 clj_S0[UNROLLJ], clj_S1[UNROLLJ], c6t_S[2], c12t_S[2];
188 for (p = 0; p < UNROLLJ; p++)
190 /* Here we load 4 aligned floats, but we need just 2 */
191 clj_S0[p] = _mm_load_ps(nbfp0+type[aj+p]*nbfp_stride);
193 for (p = 0; p < UNROLLJ; p++)
195 /* Here we load 4 aligned floats, but we need just 2 */
196 clj_S1[p] = _mm_load_ps(nbfp1+type[aj+p]*nbfp_stride);
198 gmx_shuffle_4_ps_fil01_to_2_ps(clj_S0[0], clj_S0[1], clj_S0[2], clj_S0[3],
199 &c6t_S[0], &c12t_S[0]);
200 gmx_shuffle_4_ps_fil01_to_2_ps(clj_S1[0], clj_S1[1], clj_S1[2], clj_S1[3],
201 &c6t_S[1], &c12t_S[1]);
203 *c6_S = gmx_2_mm_to_m256(c6t_S[0], c6t_S[1]);
204 *c12_S = gmx_2_mm_to_m256(c12t_S[0], c12t_S[1]);
209 /* The load_table functions below are performance critical.
210 * The routines issue UNROLLI*UNROLLJ _mm_load_ps calls.
211 * As these all have latencies, scheduling is crucial.
212 * The Intel compilers and CPUs seem to do a good job at this.
213 * But AMD CPUs perform significantly worse with gcc than with icc.
214 * Performance is improved a bit by using the extract function UNROLLJ times,
215 * instead of doing an _mm_store_si128 for every i-particle.
216 * This is only faster when we use FDV0 formatted tables, where we also need
217 * to multiple the index by 4, which can be done by a SIMD bit shift.
218 * With single precision AVX, 8 extracts are much slower than 1 store.
219 * Because of this, the load_table_f function always takes the ti
220 * parameter, which should contain a buffer that is aligned with
221 * prepare_table_load_buffer(), but it is only used with full-width
224 static gmx_inline void gmx_simdcall
225 load_table_f(const real *tab_coul_FDV0, gmx_simd_int32_t ti_S, int *ti,
226 __m256 *ctab0_S, __m256 *ctab1_S)
228 __m128 ctab_S[8], ctabt_S[4];
231 /* Bit shifting would be faster, but AVX doesn't support that */
232 _mm256_store_si256((__m256i *)ti, ti_S);
233 for (j = 0; j < 8; j++)
235 ctab_S[j] = _mm_load_ps(tab_coul_FDV0+ti[j]*4);
237 gmx_shuffle_4_ps_fil01_to_2_ps(ctab_S[0], ctab_S[1], ctab_S[2], ctab_S[3],
238 &ctabt_S[0], &ctabt_S[2]);
239 gmx_shuffle_4_ps_fil01_to_2_ps(ctab_S[4], ctab_S[5], ctab_S[6], ctab_S[7],
240 &ctabt_S[1], &ctabt_S[3]);
242 *ctab0_S = gmx_2_mm_to_m256(ctabt_S[0], ctabt_S[1]);
243 *ctab1_S = gmx_2_mm_to_m256(ctabt_S[2], ctabt_S[3]);
246 static gmx_inline void gmx_simdcall
247 load_table_f_v(const real *tab_coul_FDV0, gmx_simd_int32_t ti_S, int *ti,
248 __m256 *ctab0_S, __m256 *ctab1_S, __m256 *ctabv_S)
250 __m128 ctab_S[8], ctabt_S[4], ctabvt_S[2];
253 /* Bit shifting would be faster, but AVX doesn't support that */
254 _mm256_store_si256((__m256i *)ti, ti_S);
255 for (j = 0; j < 8; j++)
257 ctab_S[j] = _mm_load_ps(tab_coul_FDV0+ti[j]*4);
259 gmx_shuffle_4_ps_fil01_to_2_ps(ctab_S[0], ctab_S[1], ctab_S[2], ctab_S[3],
260 &ctabt_S[0], &ctabt_S[2]);
261 gmx_shuffle_4_ps_fil01_to_2_ps(ctab_S[4], ctab_S[5], ctab_S[6], ctab_S[7],
262 &ctabt_S[1], &ctabt_S[3]);
264 *ctab0_S = gmx_2_mm_to_m256(ctabt_S[0], ctabt_S[1]);
265 *ctab1_S = gmx_2_mm_to_m256(ctabt_S[2], ctabt_S[3]);
267 ctabvt_S[0] = gmx_shuffle_4_ps_fil2_to_1_ps(ctab_S[0], ctab_S[1],
268 ctab_S[2], ctab_S[3]);
269 ctabvt_S[1] = gmx_shuffle_4_ps_fil2_to_1_ps(ctab_S[4], ctab_S[5],
270 ctab_S[6], ctab_S[7]);
272 *ctabv_S = gmx_2_mm_to_m256(ctabvt_S[0], ctabvt_S[1]);
275 #ifdef GMX_SIMD_HAVE_FINT32_LOGICAL
277 typedef gmx_simd_int32_t gmx_exclfilter;
278 static const int filter_stride = GMX_SIMD_INT32_WIDTH/GMX_SIMD_REAL_WIDTH;
280 static gmx_inline gmx_exclfilter gmx_simdcall
281 gmx_load1_exclfilter(int e)
283 return _mm256_set1_epi32(e);
286 static gmx_inline gmx_exclfilter gmx_simdcall
287 gmx_load_exclusion_filter(const unsigned *i)
289 return gmx_simd_load_i(i);
292 static gmx_inline gmx_simd_bool_t gmx_simdcall
293 gmx_checkbitmask_pb(gmx_exclfilter m0, gmx_exclfilter m1)
295 return _mm256_castsi256_ps(_mm256_cmpeq_epi32(_mm256_andnot_si256(m0, m1), _mm256_setzero_si256()));
298 #else /* GMX_SIMD_HAVE_FINT32_LOGICAL */
300 /* No integer support, use a real to store the exclusion bits */
301 typedef gmx_simd_real_t gmx_exclfilter;
302 static const int filter_stride = 1;
304 static gmx_inline gmx_exclfilter gmx_simdcall
305 gmx_load1_exclfilter(int e)
307 return _mm256_castsi256_ps(_mm256_set1_epi32(e));
310 static gmx_inline gmx_exclfilter gmx_simdcall
311 gmx_load_exclusion_filter(const unsigned *i)
313 return gmx_simd_load_r((real *) (i));
316 static gmx_inline gmx_simd_bool_t gmx_simdcall
317 gmx_checkbitmask_pb(gmx_exclfilter m0, gmx_exclfilter m1)
319 return _mm256_cmp_ps(_mm256_cvtepi32_ps(_mm256_castps_si256(_mm256_and_ps(m0, m1))), _mm256_setzero_ps(), 0x0c);
322 #endif /* GMX_SIMD_HAVE_FINT32_LOGICAL */
324 #endif /* _nbnxn_kernel_simd_utils_x86_s256s_h_ */