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35 #ifndef _nbnxn_kernel_simd_utils_ref_h_
36 #define _nbnxn_kernel_simd_utils_ref_h_
38 typedef gmx_simd_ref_epi32 gmx_simd_ref_exclfilter;
39 typedef gmx_simd_ref_exclfilter gmx_exclfilter;
40 static const int filter_stride = GMX_SIMD_EPI32_WIDTH/GMX_SIMD_WIDTH_HERE;
42 /* Set the stride for the lookup of the two LJ parameters from their
43 (padded) array. Only strides of 2 and 4 are currently supported. */
44 #if defined GMX_NBNXN_SIMD_2XNN
45 static const int nbfp_stride = 4;
46 #elif defined GMX_DOUBLE
47 static const int nbfp_stride = 2;
49 static const int nbfp_stride = 4;
52 #if GMX_SIMD_WIDTH_HERE > 4
53 /* The 4xn kernel operates on 4-wide i-force registers */
55 /* float/double SIMD register type */
60 static gmx_inline gmx_mm_pr4
61 gmx_load_pr4(const real *r)
66 for (i = 0; i < 4; i++)
74 static gmx_inline void
75 gmx_store_pr4(real *dest, gmx_mm_pr4 src)
80 for (i = 0; i < 4; i++)
86 static gmx_inline gmx_mm_pr4
87 gmx_add_pr4(gmx_mm_pr4 a, gmx_mm_pr4 b)
92 for (i = 0; i < 4; i++)
94 c.r[i] = a.r[i] + b.r[i];
102 typedef gmx_simd_ref_pr gmx_simd_ref_pr4;
107 #ifdef GMX_NBNXN_SIMD_2XNN
109 /* Half-width operations are required for the 2xnn kernels */
111 /* Half-width SIMD real type */
112 /* float/double SIMD register type */
114 real r[GMX_SIMD_WIDTH_HERE/2];
117 /* Half-width SIMD operations */
119 /* Load reals at half-width aligned pointer b into half-width SIMD register a */
120 static gmx_inline void
121 gmx_load_hpr(gmx_mm_hpr *a, const real *b)
125 for (i = 0; i < GMX_SIMD_WIDTH_HERE/2; i++)
131 /* Set all entries in half-width SIMD register *a to b */
132 static gmx_inline void
133 gmx_set1_hpr(gmx_mm_hpr *a, real b)
137 for (i = 0; i < GMX_SIMD_WIDTH_HERE/2; i++)
143 /* Load one real at b and one real at b+1 into halves of a, respectively */
144 static gmx_inline void
145 gmx_load1p1_pr(gmx_simd_ref_pr *a, const real *b)
149 for (i = 0; i < GMX_SIMD_WIDTH_HERE/2; i++)
152 a->r[GMX_SIMD_WIDTH_HERE/2 + i] = b[1];
156 /* Load reals at half-width aligned pointer b into two halves of a */
157 static gmx_inline void
158 gmx_loaddh_pr(gmx_simd_ref_pr *a, const real *b)
162 for (i = 0; i < GMX_SIMD_WIDTH_HERE/2; i++)
165 a->r[GMX_SIMD_WIDTH_HERE/2 + i] = b[i];
169 /* Store half-width SIMD register b into half width aligned memory a */
170 static gmx_inline void
171 gmx_store_hpr(real *a, gmx_mm_hpr b)
175 for (i = 0; i < GMX_SIMD_WIDTH_HERE/2; i++)
181 static gmx_inline gmx_mm_hpr
182 gmx_add_hpr(gmx_mm_hpr a, gmx_mm_hpr b)
187 for (i = 0; i < GMX_SIMD_WIDTH_HERE/2; i++)
189 c.r[i] = a.r[i] + b.r[i];
195 static gmx_inline gmx_mm_hpr
196 gmx_sub_hpr(gmx_mm_hpr a, gmx_mm_hpr b)
201 for (i = 0; i < GMX_SIMD_WIDTH_HERE/2; i++)
203 c.r[i] = a.r[i] - b.r[i];
209 /* Sum over 4 half SIMD registers */
210 static gmx_inline gmx_mm_hpr
211 gmx_sum4_hpr(gmx_simd_ref_pr a, gmx_simd_ref_pr b)
216 for (i = 0; i < GMX_SIMD_WIDTH_HERE/2; i++)
220 a.r[GMX_SIMD_WIDTH_HERE/2+i] +
222 b.r[GMX_SIMD_WIDTH_HERE/2+i];
228 /* Sum the elements of halfs of each input register and store sums in out */
229 static gmx_inline gmx_mm_pr4
230 gmx_mm_transpose_sum4h_pr(gmx_simd_ref_pr a, gmx_simd_ref_pr b)
240 for (i = 0; i < GMX_SIMD_WIDTH_HERE/2; i++)
243 sum.r[1] += a.r[GMX_SIMD_WIDTH_HERE/2+i];
245 sum.r[3] += b.r[GMX_SIMD_WIDTH_HERE/2+i];
251 static gmx_inline void
252 gmx_pr_to_2hpr(gmx_simd_ref_pr a, gmx_mm_hpr *b, gmx_mm_hpr *c)
256 for (i = 0; i < GMX_SIMD_WIDTH_HERE/2; i++)
259 c->r[i] = a.r[GMX_SIMD_WIDTH_HERE/2 + i];
262 static gmx_inline void
263 gmx_2hpr_to_pr(gmx_mm_hpr a, gmx_mm_hpr b, gmx_simd_ref_pr *c)
267 for (i = 0; i < GMX_SIMD_WIDTH_HERE/2; i++)
270 c->r[GMX_SIMD_WIDTH_HERE/2 + i] = b.r[i];
274 #endif /* GMX_NBNXN_SIMD_2XNN */
278 static gmx_inline void
279 load_table_f(const real *tab_coul_F, gmx_simd_ref_epi32 ti_S, int *ti,
280 gmx_simd_ref_pr *ctab0_S, gmx_simd_ref_pr *ctab1_S)
284 for (i = 0; i < GMX_SIMD_WIDTH_HERE; i++)
286 ctab0_S->r[i] = tab_coul_F[ti_S.r[i]];
287 ctab1_S->r[i] = tab_coul_F[ti_S.r[i]+1];
290 *ctab1_S = gmx_sub_pr(*ctab1_S, *ctab0_S);
293 static gmx_inline void
294 load_table_f_v(const real *tab_coul_F, const real *tab_coul_V,
295 gmx_simd_ref_epi32 ti_S, int *ti,
296 gmx_simd_ref_pr *ctab0_S, gmx_simd_ref_pr *ctab1_S,
297 gmx_simd_ref_pr *ctabv_S)
301 load_table_f(tab_coul_F, ti_S, ti, ctab0_S, ctab1_S);
303 for (i = 0; i < GMX_SIMD_WIDTH_HERE; i++)
305 ctabv_S->r[i] = tab_coul_V[ti_S.r[i]];
311 static gmx_inline void
312 load_table_f(const real *tab_coul_FDV0, gmx_simd_ref_epi32 ti_S, int *ti,
313 gmx_simd_ref_pr *ctab0_S, gmx_simd_ref_pr *ctab1_S)
317 for (i = 0; i < GMX_SIMD_WIDTH_HERE; i++)
319 ctab0_S->r[i] = tab_coul_FDV0[ti_S.r[i]*4];
320 ctab1_S->r[i] = tab_coul_FDV0[ti_S.r[i]*4+1];
324 static gmx_inline void
325 load_table_f_v(const real *tab_coul_FDV0,
326 gmx_simd_ref_epi32 ti_S, int *ti,
327 gmx_simd_ref_pr *ctab0_S, gmx_simd_ref_pr *ctab1_S,
328 gmx_simd_ref_pr *ctabv_S)
332 load_table_f(tab_coul_FDV0, ti_S, ti, ctab0_S, ctab1_S);
334 for (i = 0; i < GMX_SIMD_WIDTH_HERE; i++)
336 ctabv_S->r[i] = tab_coul_FDV0[ti_S.r[i]*4+2];
341 /* Sum the elements within each input register and store the sums in out.
342 * Note that 4/8-way SIMD requires gmx_mm_transpose_sum4_pr instead.
344 #if GMX_SIMD_WIDTH_HERE == 2
345 static gmx_inline gmx_simd_ref_pr
346 gmx_mm_transpose_sum2_pr(gmx_simd_ref_pr in0, gmx_simd_ref_pr in1)
350 sum.r[0] = in0.r[0] + in0.r[1];
351 sum.r[1] = in1.r[0] + in1.r[1];
357 #if GMX_SIMD_WIDTH_HERE >= 4
358 #if GMX_SIMD_WIDTH_HERE == 4
359 static gmx_inline gmx_simd_ref_pr
361 static gmx_inline gmx_mm_pr4
363 gmx_mm_transpose_sum4_pr(gmx_simd_ref_pr in0, gmx_simd_ref_pr in1,
364 gmx_simd_ref_pr in2, gmx_simd_ref_pr in3)
366 #if GMX_SIMD_WIDTH_HERE == 4
378 for (i = 0; i < GMX_SIMD_WIDTH_HERE; i++)
380 sum.r[0] += in0.r[i];
381 sum.r[1] += in1.r[i];
382 sum.r[2] += in2.r[i];
383 sum.r[3] += in3.r[i];
391 /* In double precision it can be faster to first calculate single precision
392 * square roots for two double precision registers at once and then use
393 * double precision Newton-Raphson iteration to reach full double precision.
394 * For this reference code we just use a plain-C sqrt.
396 static gmx_inline void
397 gmx_mm_invsqrt2_pd(gmx_simd_ref_pr in0, gmx_simd_ref_pr in1,
398 gmx_simd_ref_pr *out0, gmx_simd_ref_pr *out1)
400 out0 = gmx_invsqrt_pr(in0);
401 out1 = gmx_invsqrt_pr(in1);
405 static gmx_inline void
406 load_lj_pair_params(const real *nbfp, const int *type, int aj,
407 gmx_simd_ref_pr *c6_S, gmx_simd_ref_pr *c12_S)
411 for (i = 0; i < GMX_SIMD_WIDTH_HERE; i++)
413 c6_S->r[i] = nbfp[type[aj+i]*nbfp_stride];
414 c12_S->r[i] = nbfp[type[aj+i]*nbfp_stride+1];
418 #ifdef GMX_NBNXN_SIMD_2XNN
419 static gmx_inline void
420 load_lj_pair_params2(const real *nbfp0, const real *nbfp1,
421 const int *type, int aj,
422 gmx_simd_ref_pr *c6_S, gmx_simd_ref_pr *c12_S)
426 for (i = 0; i < GMX_SIMD_WIDTH_HERE/2; i++)
428 c6_S->r[i] = nbfp0[type[aj+i]*nbfp_stride];
429 c6_S->r[GMX_SIMD_WIDTH_HERE/2 + i] = nbfp1[type[aj+i]*nbfp_stride];
430 c12_S->r[i] = nbfp0[type[aj+i]*nbfp_stride+1];
431 c12_S->r[GMX_SIMD_WIDTH_HERE/2 + i] = nbfp1[type[aj+i]*nbfp_stride+1];
436 /* Code for handling loading exclusions and converting them into
437 interactions. The x86 code might use either integer- or real-type
438 SIMD, but the reference code does not need to know. */
440 #define gmx_load1_exclfilter(e) gmx_simd_ref_load1_exclfilter(e)
441 #define gmx_load_exclusion_filter(e) gmx_simd_ref_load_exclusion_filter((int *) e)
442 #define gmx_checkbitmask_pb(m0, m1) gmx_simd_ref_checkbitmask_pb(m0, m1)
444 static gmx_inline gmx_simd_ref_exclfilter
445 gmx_simd_ref_load1_exclfilter(int src)
447 gmx_simd_ref_exclfilter a;
450 for (i = 0; i < GMX_SIMD_REF_WIDTH; i++)
458 static gmx_inline gmx_simd_ref_exclfilter
459 gmx_simd_ref_load_exclusion_filter(const int *src)
461 gmx_simd_ref_exclfilter a;
464 for (i = 0; i < GMX_SIMD_REF_WIDTH; i++)
472 /* For topology exclusion-pair checking we need: ((a & b) ? True :
473 * False). The x86 implementations use hardware-suitable integer-
474 * and/or real-valued SIMD operations and a bit-wise "and" to do
475 * this. The reference implementation normally uses logical operations
476 * for logic, but in this case the i- and j-atom exclusion masks
477 * computed during searching expect to be combined with bit-wise
480 * If the same bit is set in both input masks, return TRUE, else
481 * FALSE. This function is only called with a single bit set in b.
483 static gmx_inline gmx_simd_ref_pb
484 gmx_simd_ref_checkbitmask_pb(gmx_simd_ref_exclfilter a, gmx_simd_ref_exclfilter b)
489 for (i = 0; i < GMX_SIMD_REF_WIDTH; i++)
491 c.r[i] = ((a.r[i] & b.r[i]) != 0);
497 #endif /* _nbnxn_kernel_simd_utils_ref_h_ */