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37 #ifndef _nbnxn_kernel_simd_utils_h_
38 #define _nbnxn_kernel_simd_utils_h_
40 /*! \brief Provides hardware-specific utility routines for the SIMD kernels.
42 * Defines all functions, typedefs, constants and macros that have
43 * explicit dependencies on the j-cluster size, precision, or SIMD
44 * width. This includes handling diagonal, Newton and topology
47 * The functionality which depends on the j-cluster size is:
50 * energy group pair energy storage
53 #if !defined GMX_NBNXN_SIMD_2XNN && !defined GMX_NBNXN_SIMD_4XN
54 #error "Must define an NBNxN kernel flavour before including NBNxN kernel utility functions"
57 #ifdef GMX_SIMD_REFERENCE_PLAIN_C
59 /* Align a stack-based thread-local working array. */
60 static gmx_inline int *
61 prepare_table_load_buffer(const int *array)
66 #include "nbnxn_kernel_simd_utils_ref.h"
68 #else /* GMX_SIMD_REFERENCE_PLAIN_C */
71 /* Include x86 SSE2 compatible SIMD functions */
73 /* Set the stride for the lookup of the two LJ parameters from their
74 * (padded) array. We use the minimum supported SIMD memory alignment.
76 #if defined GMX_DOUBLE
77 static const int nbfp_stride = 2;
79 static const int nbfp_stride = 4;
82 /* Align a stack-based thread-local working array. Table loads on
83 * full-width AVX_256 use the array, but other implementations do
85 static gmx_inline int *
86 prepare_table_load_buffer(const int *array)
88 #if defined GMX_X86_AVX_256 && !defined GMX_USE_HALF_WIDTH_SIMD_HERE
89 return gmx_simd_align_int(array);
95 #if defined GMX_X86_AVX_256 && !defined GMX_USE_HALF_WIDTH_SIMD_HERE
97 /* With full AVX-256 SIMD, half SIMD-width table loads are optimal */
98 #if GMX_SIMD_WIDTH_HERE == 8
103 Berk, 2xnn.c had the following code, but I think it is safe to remove now, given the code immediately above.
105 #if defined GMX_X86_AVX_256 && !defined GMX_DOUBLE
106 / * AVX-256 single precision 2x(4+4) kernel,
107 * we can do half SIMD-width aligned FDV0 table loads.
114 #include "nbnxn_kernel_simd_utils_x86_256d.h"
115 #else /* GMX_DOUBLE */
116 #include "nbnxn_kernel_simd_utils_x86_256s.h"
117 #endif /* GMX_DOUBLE */
119 #else /* defined GMX_X86_AVX_256 && !defined GMX_USE_HALF_WIDTH_SIMD_HERE */
121 /* We use the FDV0 table layout when we can use aligned table loads */
122 #if GMX_SIMD_WIDTH_HERE == 4
127 #include "nbnxn_kernel_simd_utils_x86_128d.h"
128 #else /* GMX_DOUBLE */
129 #include "nbnxn_kernel_simd_utils_x86_128s.h"
130 #endif /* GMX_DOUBLE */
132 #endif /* defined GMX_X86_AVX_256 && !defined GMX_USE_HALF_WIDTH_SIMD_HERE */
134 #else /* GMX_X86_SSE2 */
136 #if GMX_SIMD_WIDTH_HERE > 4
137 static const int nbfp_stride = 4;
139 static const int nbfp_stride = GMX_SIMD_WIDTH_HERE;
142 /* We use the FDV0 table layout when we can use aligned table loads */
143 #if GMX_SIMD_WIDTH_HERE == 4
147 #ifdef GMX_CPU_ACCELERATION_IBM_QPX
148 #include "nbnxn_kernel_simd_utils_ibm_qpx.h"
149 #endif /* GMX_CPU_ACCELERATION_IBM_QPX */
151 #endif /* GMX_X86_SSE2 */
152 #endif /* GMX_SIMD_REFERENCE_PLAIN_C */
156 /* Add energy register to possibly multiple terms in the energy array */
157 static inline void add_ener_grp(gmx_mm_pr e_S, real *v, const int *offset_jj)
161 /* We need to balance the number of store operations with
162 * the rapidly increases number of combinations of energy groups.
163 * We add to a temporary buffer for 1 i-group vs 2 j-groups.
165 for (jj = 0; jj < (UNROLLJ/2); jj++)
169 v_S = gmx_load_pr(v+offset_jj[jj]+jj*GMX_SIMD_WIDTH_HERE);
170 gmx_store_pr(v+offset_jj[jj]+jj*GMX_SIMD_WIDTH_HERE, gmx_add_pr(v_S, e_S));
175 #if defined GMX_NBNXN_SIMD_2XNN && defined UNROLLJ
176 /* As add_ener_grp, but for two groups of UNROLLJ/2 stored in
177 * a single SIMD register.
180 add_ener_grp_halves(gmx_mm_pr e_S, real *v0, real *v1, const int *offset_jj)
182 gmx_mm_hpr e_S0, e_S1;
185 gmx_pr_to_2hpr(e_S, &e_S0, &e_S1);
187 for (jj = 0; jj < (UNROLLJ/2); jj++)
191 gmx_load_hpr(&v_S, v0+offset_jj[jj]+jj*GMX_SIMD_WIDTH_HERE/2);
192 gmx_store_hpr(v0+offset_jj[jj]+jj*GMX_SIMD_WIDTH_HERE/2, gmx_add_hpr(v_S, e_S0));
194 for (jj = 0; jj < (UNROLLJ/2); jj++)
198 gmx_load_hpr(&v_S, v1+offset_jj[jj]+jj*GMX_SIMD_WIDTH_HERE/2);
199 gmx_store_hpr(v1+offset_jj[jj]+jj*GMX_SIMD_WIDTH_HERE/2, gmx_add_hpr(v_S, e_S1));
204 #endif /* _nbnxn_kernel_simd_utils_h_ */