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35 #ifndef _nbnxn_kernel_simd_utils_h_
36 #define _nbnxn_kernel_simd_utils_h_
38 /*! \brief Provides hardware-specific utility routines for the SIMD kernels.
40 * Defines all functions, typedefs, constants and macros that have
41 * explicit dependencies on the j-cluster size, precision, or SIMD
42 * width. This includes handling diagonal, Newton and topology
45 * The functionality which depends on the j-cluster size is:
48 * energy group pair energy storage
51 #if !defined GMX_NBNXN_SIMD_2XNN && !defined GMX_NBNXN_SIMD_4XN
52 #error "Must define an NBNxN kernel flavour before including NBNxN kernel utility functions"
55 #ifdef GMX_SIMD_REFERENCE_PLAIN_C
57 /* Align a stack-based thread-local working array. */
58 static gmx_inline int *
59 prepare_table_load_buffer(const int *array)
64 #include "nbnxn_kernel_simd_utils_ref.h"
66 #else /* GMX_SIMD_REFERENCE_PLAIN_C */
69 /* Include x86 SSE2 compatible SIMD functions */
71 /* Set the stride for the lookup of the two LJ parameters from their
72 * (padded) array. We use the minimum supported SIMD memory alignment.
74 #if defined GMX_DOUBLE
75 static const int nbfp_stride = 2;
77 static const int nbfp_stride = 4;
80 /* Align a stack-based thread-local working array. Table loads on
81 * full-width AVX_256 use the array, but other implementations do
83 static gmx_inline int *
84 prepare_table_load_buffer(const int *array)
86 #if defined GMX_X86_AVX_256 && !defined GMX_USE_HALF_WIDTH_SIMD_HERE
87 return gmx_simd_align_int(array);
93 #if defined GMX_X86_AVX_256 && !defined GMX_USE_HALF_WIDTH_SIMD_HERE
95 /* With full AVX-256 SIMD, half SIMD-width table loads are optimal */
96 #if GMX_SIMD_WIDTH_HERE == 8
101 #include "nbnxn_kernel_simd_utils_x86_256d.h"
102 #else /* GMX_DOUBLE */
103 #include "nbnxn_kernel_simd_utils_x86_256s.h"
104 #endif /* GMX_DOUBLE */
106 #else /* defined GMX_X86_AVX_256 && !defined GMX_USE_HALF_WIDTH_SIMD_HERE */
108 /* We use the FDV0 table layout when we can use aligned table loads */
109 #if GMX_SIMD_WIDTH_HERE == 4
114 #include "nbnxn_kernel_simd_utils_x86_128d.h"
115 #else /* GMX_DOUBLE */
116 #include "nbnxn_kernel_simd_utils_x86_128s.h"
117 #endif /* GMX_DOUBLE */
119 #endif /* defined GMX_X86_AVX_256 && !defined GMX_USE_HALF_WIDTH_SIMD_HERE */
121 #else /* GMX_X86_SSE2 */
123 #if GMX_SIMD_WIDTH_HERE > 4
124 static const int nbfp_stride = 4;
126 static const int nbfp_stride = GMX_SIMD_WIDTH_HERE;
129 /* We use the FDV0 table layout when we can use aligned table loads */
130 #if GMX_SIMD_WIDTH_HERE == 4
134 #ifdef GMX_CPU_ACCELERATION_IBM_QPX
135 #include "nbnxn_kernel_simd_utils_ibm_qpx.h"
136 #endif /* GMX_CPU_ACCELERATION_IBM_QPX */
138 #endif /* GMX_X86_SSE2 */
139 #endif /* GMX_SIMD_REFERENCE_PLAIN_C */
143 /* Add energy register to possibly multiple terms in the energy array */
144 static inline void add_ener_grp(gmx_mm_pr e_S, real *v, const int *offset_jj)
148 /* We need to balance the number of store operations with
149 * the rapidly increases number of combinations of energy groups.
150 * We add to a temporary buffer for 1 i-group vs 2 j-groups.
152 for (jj = 0; jj < (UNROLLJ/2); jj++)
156 v_S = gmx_load_pr(v+offset_jj[jj]+jj*GMX_SIMD_WIDTH_HERE);
157 gmx_store_pr(v+offset_jj[jj]+jj*GMX_SIMD_WIDTH_HERE, gmx_add_pr(v_S, e_S));
162 #if defined GMX_NBNXN_SIMD_2XNN && defined UNROLLJ
163 /* As add_ener_grp, but for two groups of UNROLLJ/2 stored in
164 * a single SIMD register.
167 add_ener_grp_halves(gmx_mm_pr e_S, real *v0, real *v1, const int *offset_jj)
169 gmx_mm_hpr e_S0, e_S1;
172 gmx_pr_to_2hpr(e_S, &e_S0, &e_S1);
174 for (jj = 0; jj < (UNROLLJ/2); jj++)
178 gmx_load_hpr(&v_S, v0+offset_jj[jj]+jj*GMX_SIMD_WIDTH_HERE/2);
179 gmx_store_hpr(v0+offset_jj[jj]+jj*GMX_SIMD_WIDTH_HERE/2, gmx_add_hpr(v_S, e_S0));
181 for (jj = 0; jj < (UNROLLJ/2); jj++)
185 gmx_load_hpr(&v_S, v1+offset_jj[jj]+jj*GMX_SIMD_WIDTH_HERE/2);
186 gmx_store_hpr(v1+offset_jj[jj]+jj*GMX_SIMD_WIDTH_HERE/2, gmx_add_hpr(v_S, e_S1));
191 #endif /* _nbnxn_kernel_simd_utils_h_ */