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38 /* The macros in this file are intended to be used for writing
39 * architecture-independent SIMD intrinsics code.
40 * To support a new architecture, adding macros here should be (nearly)
44 #ifdef _gmx_simd_macros_h_
45 #error "gmx_simd_macros.h included twice"
47 #define _gmx_simd_macros_h_
49 /* NOTE: SSE2 acceleration does not include floor or blendv */
52 /* Uncomment the next line, without other SIMD active, for testing plain-C */
53 /* #define GMX_SIMD_REFERENCE_PLAIN_C */
54 #ifdef GMX_SIMD_REFERENCE_PLAIN_C
55 /* Plain C SIMD reference implementation, also serves as documentation */
56 #define GMX_HAVE_SIMD_MACROS
58 /* In general the reference SIMD supports any SIMD width, including 1.
59 * For the nbnxn 4xn kernels all widths (2, 4 and 8) are supported.
60 * The nbnxn 2xnn kernels are currently not supported.
62 #define GMX_SIMD_REF_WIDTH 4
64 /* Include plain-C reference implementation, also serves as documentation */
65 #include "gmx_simd_ref.h"
67 #define GMX_SIMD_WIDTH_HERE GMX_SIMD_REF_WIDTH
69 /* float/double SIMD register type */
70 #define gmx_mm_pr gmx_simd_ref_pr
72 /* boolean SIMD register type */
73 #define gmx_mm_pb gmx_simd_ref_pb
75 /* integer SIMD register type, only for table indexing and exclusion masks */
76 #define gmx_epi32 gmx_simd_ref_epi32
77 #define GMX_SIMD_EPI32_WIDTH GMX_SIMD_REF_EPI32_WIDTH
79 /* Load GMX_SIMD_WIDTH_HERE reals for memory starting at r */
80 #define gmx_load_pr gmx_simd_ref_load_pr
81 /* Set all SIMD register elements to *r */
82 #define gmx_load1_pr gmx_simd_ref_load1_pr
83 #define gmx_set1_pr gmx_simd_ref_set1_pr
84 #define gmx_setzero_pr gmx_simd_ref_setzero_pr
85 #define gmx_store_pr gmx_simd_ref_store_pr
87 #define gmx_add_pr gmx_simd_ref_add_pr
88 #define gmx_sub_pr gmx_simd_ref_sub_pr
89 #define gmx_mul_pr gmx_simd_ref_mul_pr
90 /* For the FMA macros below, aim for c=d in code, so FMA3 uses 1 instruction */
91 #define gmx_madd_pr gmx_simd_ref_madd_pr
92 #define gmx_nmsub_pr gmx_simd_ref_nmsub_pr
94 #define gmx_max_pr gmx_simd_ref_max_pr
95 #define gmx_blendzero_pr gmx_simd_ref_blendzero_pr
97 #define gmx_round_pr gmx_simd_ref_round_pr
99 /* Not required, only used to speed up the nbnxn tabulated PME kernels */
100 #define GMX_SIMD_HAVE_FLOOR
101 #ifdef GMX_SIMD_HAVE_FLOOR
102 #define gmx_floor_pr gmx_simd_ref_floor_pr
105 /* Not required, only used when blendv is faster than comparison */
106 #define GMX_SIMD_HAVE_BLENDV
107 #ifdef GMX_SIMD_HAVE_BLENDV
108 #define gmx_blendv_pr gmx_simd_ref_blendv_pr
111 /* Copy the sign of a to b, assumes b >= 0 for efficiency */
112 #define gmx_cpsgn_nonneg_pr gmx_simd_ref_cpsgn_nonneg_pr
114 /* Very specific operation required in the non-bonded kernels */
115 #define gmx_masknot_add_pr gmx_simd_ref_masknot_add_pr
118 #define gmx_cmplt_pr gmx_simd_ref_cmplt_pr
120 /* Logical operations on SIMD booleans */
121 #define gmx_and_pb gmx_simd_ref_and_pb
122 #define gmx_or_pb gmx_simd_ref_or_pb
124 /* Not required, gmx_anytrue_pb(x) returns if any of the boolean is x is True.
125 * If this is not present, define GMX_SIMD_IS_TRUE(real x),
126 * which should return x==True, where True is True as defined in SIMD.
128 #define GMX_SIMD_HAVE_ANYTRUE
129 #ifdef GMX_SIMD_HAVE_ANYTRUE
130 #define gmx_anytrue_pb gmx_simd_ref_anytrue_pb
132 /* If we don't have gmx_anytrue_pb, we need to store gmx_mm_pb */
133 #define gmx_store_pb gmx_simd_ref_store_pb
136 /* Conversions only used for PME table lookup */
137 #define gmx_cvttpr_epi32 gmx_simd_ref_cvttpr_epi32
138 #define gmx_cvtepi32_pr gmx_simd_ref_cvtepi32_pr
140 /* These two function only need to be approximate, Newton-Raphson iteration
141 * is used for full accuracy in gmx_invsqrt_pr and gmx_inv_pr.
143 #define gmx_rsqrt_pr gmx_simd_ref_rsqrt_pr
144 #define gmx_rcp_pr gmx_simd_ref_rcp_pr
146 /* sqrt+inv+sin+cos+acos+atan2 are used for bonded potentials, exp for PME */
147 #define GMX_SIMD_HAVE_EXP
148 #ifdef GMX_SIMD_HAVE_EXP
149 #define gmx_exp_pr gmx_simd_ref_exp_pr
151 #define GMX_SIMD_HAVE_TRIGONOMETRIC
152 #ifdef GMX_SIMD_HAVE_TRIGONOMETRIC
153 #define gmx_sqrt_pr gmx_simd_ref_sqrt_pr
154 #define gmx_sincos_pr gmx_simd_ref_sincos_pr
155 #define gmx_acos_pr gmx_simd_ref_acos_pr
156 #define gmx_atan2_pr gmx_simd_ref_atan2_pr
159 #endif /* GMX_SIMD_REFERENCE_PLAIN_C */
162 /* The same SIMD macros can be translated to SIMD intrinsics (and compiled
163 * to instructions for) different SIMD width and float precision.
165 * On x86: The gmx_ prefix is replaced by _mm_ or _mm256_ (SSE or AVX).
166 * The _pr suffix is replaced by _ps or _pd (for single or double precision).
167 * Compiler settings will decide if 128-bit intrinsics will
168 * be translated into SSE or AVX instructions.
172 #ifdef GMX_USE_HALF_WIDTH_SIMD_HERE
173 #if defined GMX_X86_AVX_256
174 /* We have half SIMD width support, continue */
176 #error "half SIMD width intrinsics are not supported"
182 /* This is for general x86 SIMD instruction sets that also support SSE2 */
183 #define GMX_HAVE_SIMD_MACROS
185 /* Include the highest supported x86 SIMD intrisics + math functions */
186 #ifdef GMX_X86_AVX_256
187 #include "gmx_x86_avx_256.h"
189 #include "gmx_math_x86_avx_256_double.h"
191 #include "gmx_math_x86_avx_256_single.h"
194 #ifdef GMX_X86_AVX_128_FMA
195 #include "gmx_x86_avx_128_fma.h"
197 #include "gmx_math_x86_avx_128_fma_double.h"
199 #include "gmx_math_x86_avx_128_fma_single.h"
202 #ifdef GMX_X86_SSE4_1
203 #include "gmx_x86_sse4_1.h"
205 #include "gmx_math_x86_sse4_1_double.h"
207 #include "gmx_math_x86_sse4_1_single.h"
211 #include "gmx_x86_sse2.h"
213 #include "gmx_math_x86_sse2_double.h"
215 #include "gmx_math_x86_sse2_single.h"
218 #error No x86 acceleration defined
223 /* exp and trigonometric functions are included above */
224 #define GMX_SIMD_HAVE_EXP
225 #define GMX_SIMD_HAVE_TRIGONOMETRIC
227 #if !defined GMX_X86_AVX_256 || defined GMX_USE_HALF_WIDTH_SIMD_HERE
231 #define GMX_SIMD_WIDTH_HERE 4
233 #define gmx_mm_pr __m128
235 #define gmx_mm_pb __m128
237 #define gmx_epi32 __m128i
238 #define GMX_SIMD_EPI32_WIDTH 4
240 #define gmx_load_pr _mm_load_ps
241 #define gmx_load1_pr _mm_load1_ps
242 #define gmx_set1_pr _mm_set1_ps
243 #define gmx_setzero_pr _mm_setzero_ps
244 #define gmx_store_pr _mm_store_ps
246 #define gmx_add_pr _mm_add_ps
247 #define gmx_sub_pr _mm_sub_ps
248 #define gmx_mul_pr _mm_mul_ps
249 #ifdef GMX_X86_AVX_128_FMA
250 #define GMX_SIMD_HAVE_FMA
251 #define gmx_madd_pr(a, b, c) _mm_macc_ps(a, b, c)
252 #define gmx_nmsub_pr(a, b, c) _mm_nmacc_ps(a, b, c)
254 #define gmx_madd_pr(a, b, c) _mm_add_ps(c, _mm_mul_ps(a, b))
255 #define gmx_nmsub_pr(a, b, c) _mm_sub_ps(c, _mm_mul_ps(a, b))
257 #define gmx_max_pr _mm_max_ps
258 #define gmx_blendzero_pr _mm_and_ps
260 #define gmx_cmplt_pr _mm_cmplt_ps
261 #define gmx_and_pb _mm_and_ps
262 #define gmx_or_pb _mm_or_ps
264 #ifdef GMX_X86_SSE4_1
265 #define gmx_round_pr(x) _mm_round_ps(x, 0x0)
266 #define GMX_SIMD_HAVE_FLOOR
267 #define gmx_floor_pr _mm_floor_ps
269 #define gmx_round_pr(x) _mm_cvtepi32_ps(_mm_cvtps_epi32(x))
272 #ifdef GMX_X86_SSE4_1
273 #define GMX_SIMD_HAVE_BLENDV
274 #define gmx_blendv_pr _mm_blendv_ps
277 static gmx_inline gmx_mm_pr gmx_cpsgn_nonneg_pr(gmx_mm_pr a, gmx_mm_pr b)
279 /* The value -0.0 has only the sign-bit set */
280 gmx_mm_pr sign_mask = _mm_set1_ps(-0.0);
281 return _mm_or_ps(_mm_and_ps(a, sign_mask), b);
284 static gmx_inline gmx_mm_pr gmx_masknot_add_pr(gmx_mm_pb a, gmx_mm_pr b, gmx_mm_pr c) { return _mm_add_ps(b, _mm_andnot_ps(a, c)); };
286 #define GMX_SIMD_HAVE_ANYTRUE
287 #define gmx_anytrue_pb _mm_movemask_ps
289 #define gmx_cvttpr_epi32 _mm_cvttps_epi32
290 #define gmx_cvtepi32_pr _mm_cvtepi32_ps
292 #define gmx_rsqrt_pr _mm_rsqrt_ps
293 #define gmx_rcp_pr _mm_rcp_ps
295 #define gmx_exp_pr gmx_mm_exp_ps
296 #define gmx_sqrt_pr gmx_mm_sqrt_ps
297 #define gmx_sincos_pr gmx_mm_sincos_ps
298 #define gmx_acos_pr gmx_mm_acos_ps
299 #define gmx_atan2_pr gmx_mm_atan2_ps
301 #else /* ifndef GMX_DOUBLE */
303 #define GMX_SIMD_WIDTH_HERE 2
305 #define gmx_mm_pr __m128d
307 #define gmx_mm_pb __m128d
309 #define gmx_epi32 __m128i
310 #define GMX_SIMD_EPI32_WIDTH 4
312 #define gmx_load_pr _mm_load_pd
313 #define gmx_load1_pr _mm_load1_pd
314 #define gmx_set1_pr _mm_set1_pd
315 #define gmx_setzero_pr _mm_setzero_pd
316 #define gmx_store_pr _mm_store_pd
318 #define gmx_add_pr _mm_add_pd
319 #define gmx_sub_pr _mm_sub_pd
320 #define gmx_mul_pr _mm_mul_pd
321 #ifdef GMX_X86_AVX_128_FMA
322 #define GMX_SIMD_HAVE_FMA
323 #define gmx_madd_pr(a, b, c) _mm_macc_pd(a, b, c)
324 #define gmx_nmsub_pr(a, b, c) _mm_nmacc_pd(a, b, c)
326 #define gmx_madd_pr(a, b, c) _mm_add_pd(c, _mm_mul_pd(a, b))
327 #define gmx_nmsub_pr(a, b, c) _mm_sub_pd(c, _mm_mul_pd(a, b))
329 #define gmx_max_pr _mm_max_pd
330 #define gmx_blendzero_pr _mm_and_pd
332 #ifdef GMX_X86_SSE4_1
333 #define gmx_round_pr(x) _mm_round_pd(x, 0x0)
334 #define GMX_SIMD_HAVE_FLOOR
335 #define gmx_floor_pr _mm_floor_pd
337 #define gmx_round_pr(x) _mm_cvtepi32_pd(_mm_cvtpd_epi32(x))
338 /* gmx_floor_pr is not used in code for pre-SSE4_1 hardware */
341 #ifdef GMX_X86_SSE4_1
342 #define GMX_SIMD_HAVE_BLENDV
343 #define gmx_blendv_pr _mm_blendv_pd
346 static gmx_inline gmx_mm_pr gmx_cpsgn_nonneg_pr(gmx_mm_pr a, gmx_mm_pr b)
348 gmx_mm_pr sign_mask = _mm_set1_pd(-0.0);
349 return _mm_or_pd(_mm_and_pd(a, sign_mask), b);
352 static gmx_inline gmx_mm_pr gmx_masknot_add_pr(gmx_mm_pb a, gmx_mm_pr b, gmx_mm_pr c) { return _mm_add_pd(b, _mm_andnot_pd(a, c)); };
354 #define gmx_cmplt_pr _mm_cmplt_pd
356 #define gmx_and_pb _mm_and_pd
357 #define gmx_or_pb _mm_or_pd
359 #define GMX_SIMD_HAVE_ANYTRUE
360 #define gmx_anytrue_pb _mm_movemask_pd
362 #define gmx_cvttpr_epi32 _mm_cvttpd_epi32
363 #define gmx_cvtepi32_pr _mm_cvtepi32_pd
365 #define gmx_rsqrt_pr(r) _mm_cvtps_pd(_mm_rsqrt_ps(_mm_cvtpd_ps(r)))
366 #define gmx_rcp_pr(r) _mm_cvtps_pd(_mm_rcp_ps(_mm_cvtpd_ps(r)))
368 #define gmx_exp_pr gmx_mm_exp_pd
369 #define gmx_sqrt_pr gmx_mm_sqrt_pd
370 #define gmx_sincos_pr gmx_mm_sincos_pd
371 #define gmx_acos_pr gmx_mm_acos_pd
372 #define gmx_atan2_pr gmx_mm_atan2_pd
374 #endif /* ifndef GMX_DOUBLE */
377 /* We have GMX_X86_AVX_256 and not GMX_USE_HALF_WIDTH_SIMD_HERE,
378 * so we use 256-bit SIMD.
383 #define GMX_SIMD_WIDTH_HERE 8
385 #define gmx_mm_pr __m256
387 #define gmx_mm_pb __m256
389 #define gmx_epi32 __m256i
390 #define GMX_SIMD_EPI32_WIDTH 8
392 #define gmx_load_pr _mm256_load_ps
393 #define gmx_load1_pr(x) _mm256_set1_ps((x)[0])
394 #define gmx_set1_pr _mm256_set1_ps
395 #define gmx_setzero_pr _mm256_setzero_ps
396 #define gmx_store_pr _mm256_store_ps
398 #define gmx_add_pr _mm256_add_ps
399 #define gmx_sub_pr _mm256_sub_ps
400 #define gmx_mul_pr _mm256_mul_ps
401 #define gmx_madd_pr(a, b, c) _mm256_add_ps(c, _mm256_mul_ps(a, b))
402 #define gmx_nmsub_pr(a, b, c) _mm256_sub_ps(c, _mm256_mul_ps(a, b))
403 #define gmx_max_pr _mm256_max_ps
404 #define gmx_blendzero_pr _mm256_and_ps
406 #define gmx_round_pr(x) _mm256_round_ps(x, 0x0)
407 #define GMX_SIMD_HAVE_FLOOR
408 #define gmx_floor_pr _mm256_floor_ps
410 #define GMX_SIMD_HAVE_BLENDV
411 #define gmx_blendv_pr _mm256_blendv_ps
413 static gmx_inline gmx_mm_pr gmx_cpsgn_nonneg_pr(gmx_mm_pr a, gmx_mm_pr b)
415 gmx_mm_pr sign_mask = _mm256_set1_ps(-0.0);
416 return _mm256_or_ps(_mm256_and_ps(a, sign_mask), b);
419 static gmx_inline gmx_mm_pr gmx_masknot_add_pr(gmx_mm_pb a, gmx_mm_pr b, gmx_mm_pr c) { return _mm256_add_ps(b, _mm256_andnot_ps(a, c)); };
421 /* Less-than (we use ordered, non-signaling, but that's not required) */
422 #define gmx_cmplt_pr(x, y) _mm256_cmp_ps(x, y, 0x11)
423 #define gmx_and_pb _mm256_and_ps
424 #define gmx_or_pb _mm256_or_ps
426 #define GMX_SIMD_HAVE_ANYTRUE
427 #define gmx_anytrue_pb _mm256_movemask_ps
429 #define gmx_cvttpr_epi32 _mm256_cvttps_epi32
431 #define gmx_rsqrt_pr _mm256_rsqrt_ps
432 #define gmx_rcp_pr _mm256_rcp_ps
434 #define gmx_exp_pr gmx_mm256_exp_ps
435 #define gmx_sqrt_pr gmx_mm256_sqrt_ps
436 #define gmx_sincos_pr gmx_mm256_sincos_ps
437 #define gmx_acos_pr gmx_mm256_acos_ps
438 #define gmx_atan2_pr gmx_mm256_atan2_ps
440 #else /* ifndef GMX_DOUBLE */
442 #define GMX_SIMD_WIDTH_HERE 4
444 #define gmx_mm_pr __m256d
446 #define gmx_mm_pb __m256d
448 /* We use 128-bit integer registers because of missing 256-bit operations */
449 #define gmx_epi32 __m128i
450 #define GMX_SIMD_EPI32_WIDTH 4
452 #define gmx_load_pr _mm256_load_pd
453 #define gmx_load1_pr(x) _mm256_set1_pd((x)[0])
454 #define gmx_set1_pr _mm256_set1_pd
455 #define gmx_setzero_pr _mm256_setzero_pd
456 #define gmx_store_pr _mm256_store_pd
458 #define gmx_add_pr _mm256_add_pd
459 #define gmx_sub_pr _mm256_sub_pd
460 #define gmx_mul_pr _mm256_mul_pd
461 #define gmx_madd_pr(a, b, c) _mm256_add_pd(c, _mm256_mul_pd(a, b))
462 #define gmx_nmsub_pr(a, b, c) _mm256_sub_pd(c, _mm256_mul_pd(a, b))
463 #define gmx_max_pr _mm256_max_pd
464 #define gmx_blendzero_pr _mm256_and_pd
466 #define gmx_round_pr(x) _mm256_round_pd(x, 0x0)
467 #define GMX_SIMD_HAVE_FLOOR
468 #define gmx_floor_pr _mm256_floor_pd
470 #define GMX_SIMD_HAVE_BLENDV
471 #define gmx_blendv_pr _mm256_blendv_pd
473 static gmx_inline gmx_mm_pr gmx_cpsgn_nonneg_pr(gmx_mm_pr a, gmx_mm_pr b)
475 gmx_mm_pr sign_mask = _mm256_set1_pd(-0.0);
476 return _mm256_or_pd(_mm256_and_pd(a, sign_mask), b);
479 static gmx_inline gmx_mm_pr gmx_masknot_add_pr(gmx_mm_pb a, gmx_mm_pr b, gmx_mm_pr c) { return _mm256_add_pd(b, _mm256_andnot_pd(a, c)); };
481 /* Less-than (we use ordered, non-signaling, but that's not required) */
482 #define gmx_cmplt_pr(x, y) _mm256_cmp_pd(x, y, 0x11)
484 #define gmx_and_pb _mm256_and_pd
485 #define gmx_or_pb _mm256_or_pd
487 #define GMX_SIMD_HAVE_ANYTRUE
488 #define gmx_anytrue_pb _mm256_movemask_pd
490 #define gmx_cvttpr_epi32 _mm256_cvttpd_epi32
492 #define gmx_rsqrt_pr(r) _mm256_cvtps_pd(_mm_rsqrt_ps(_mm256_cvtpd_ps(r)))
493 #define gmx_rcp_pr(r) _mm256_cvtps_pd(_mm_rcp_ps(_mm256_cvtpd_ps(r)))
495 #define gmx_exp_pr gmx_mm256_exp_pd
496 #define gmx_sqrt_pr gmx_mm256_sqrt_pd
497 #define gmx_sincos_pr gmx_mm256_sincos_pd
498 #define gmx_acos_pr gmx_mm256_acos_pd
499 #define gmx_atan2_pr gmx_mm256_atan2_pd
501 #endif /* ifndef GMX_DOUBLE */
503 #endif /* 128- or 256-bit x86 SIMD */
505 #endif /* GMX_X86_SSE2 */
508 #ifdef GMX_HAVE_SIMD_MACROS
509 /* Generic functions to extract a SIMD aligned pointer from a pointer x.
510 * x should have at least GMX_SIMD_WIDTH_HERE elements extra compared
511 * to how many you want to use, to avoid indexing outside the aligned region.
514 static gmx_inline real *
515 gmx_simd_align_real(const real *x)
517 return (real *)(((size_t)((x)+GMX_SIMD_WIDTH_HERE)) & (~((size_t)(GMX_SIMD_WIDTH_HERE*sizeof(real)-1))));
520 static gmx_inline int *
521 gmx_simd_align_int(const int *x)
523 return (int *)(((size_t)((x)+GMX_SIMD_WIDTH_HERE)) & (~((size_t)(GMX_SIMD_WIDTH_HERE*sizeof(int )-1))));
527 /* Include the math functions which only need the above macros,
528 * generally these are the ones that don't need masking operations.
531 #include "gmx_simd_math_double.h"
533 #include "gmx_simd_math_single.h"
536 #endif /* GMX_HAVE_SIMD_MACROS */
538 #endif /* _gmx_simd_macros_h_ */