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49 /* MSVC definition for __cpuid() */
51 /* sysinfo functions */
55 /* sysconf() definition */
59 #include "gmx_cpuid.h"
63 /* For convenience, and to enable configure-time invocation, we keep all architectures
64 * in a single file, but to avoid repeated ifdefs we set the overall architecture here.
67 /* OK, it is x86, but can we execute cpuid? */
68 #if defined(GMX_X86_GCC_INLINE_ASM) || ( defined(_MSC_VER) && ( (_MSC_VER > 1500) || (_MSC_VER == 1500 & _MSC_FULL_VER >= 150030729)))
69 # define GMX_CPUID_X86
73 /* Global constant character strings corresponding to our enumerated types */
75 gmx_cpuid_vendor_string[GMX_CPUID_NVENDORS] =
86 gmx_cpuid_vendor_string_alternative[GMX_CPUID_NVENDORS] =
93 "ibm" /* Used on BlueGene/Q */
97 gmx_cpuid_feature_string[GMX_CPUID_NFEATURES] =
137 gmx_cpuid_simd_string[GMX_CPUID_NSIMD] =
151 /* Max length of brand string */
152 #define GMX_CPUID_BRAND_MAXLEN 256
155 /* Contents of the abstract datatype */
158 enum gmx_cpuid_vendor vendor;
159 char brand[GMX_CPUID_BRAND_MAXLEN];
163 /* Not using gmx_bool here, since this file must be possible to compile without simple.h */
164 char feature[GMX_CPUID_NFEATURES];
166 /* Basic CPU topology information. For x86 this is a bit complicated since the topology differs between
167 * operating systems and sometimes even settings. For most other architectures you can likely just check
168 * the documentation and then write static information to these arrays rather than detecting on-the-fly.
170 int have_cpu_topology;
171 int nproc; /* total number of logical processors from OS */
173 int ncores_per_package;
174 int nhwthreads_per_core;
176 int * core_id; /* Local core id in each package */
177 int * hwthread_id; /* Local hwthread id in each core */
178 int * locality_order; /* Processor indices sorted in locality order */
182 /* Simple routines to access the data structure. The initialization routine is
183 * further down since that needs to call other static routines in this file.
185 enum gmx_cpuid_vendor
186 gmx_cpuid_vendor (gmx_cpuid_t cpuid)
188 return cpuid->vendor;
193 gmx_cpuid_brand (gmx_cpuid_t cpuid)
199 gmx_cpuid_family (gmx_cpuid_t cpuid)
201 return cpuid->family;
205 gmx_cpuid_model (gmx_cpuid_t cpuid)
211 gmx_cpuid_stepping (gmx_cpuid_t cpuid)
213 return cpuid->stepping;
217 gmx_cpuid_feature (gmx_cpuid_t cpuid,
218 enum gmx_cpuid_feature feature)
220 return (cpuid->feature[feature] != 0);
226 /* What type of SIMD was compiled in, if any? */
227 #ifdef GMX_SIMD_X86_AVX2_256
228 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_X86_AVX2_256;
229 #elif defined GMX_SIMD_X86_AVX_256
230 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_X86_AVX_256;
231 #elif defined GMX_SIMD_X86_AVX_128_FMA
232 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_X86_AVX_128_FMA;
233 #elif defined GMX_SIMD_X86_SSE4_1
234 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_X86_SSE4_1;
235 #elif defined GMX_SIMD_X86_SSE2
236 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_X86_SSE2;
237 #elif defined GMX_SIMD_SPARC64_HPC_ACE
238 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_SPARC64_HPC_ACE;
239 #elif defined GMX_SIMD_IBM_QPX
240 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_IBM_QPX;
241 #elif defined GMX_SIMD_REFERENCE
242 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_REFERENCE;
244 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_NONE;
250 /* Execute CPUID on x86 class CPUs. level sets function to exec, and the
251 * contents of register output is returned. See Intel/AMD docs for details.
253 * This version supports extended information where we can also have an input
254 * value in the ecx register. This is ignored for most levels, but some of them
255 * (e.g. level 0xB on Intel) use it.
258 execute_x86cpuid(unsigned int level,
267 /* Currently CPUID is only supported (1) if we can use an instruction on MSVC, or (2)
268 * if the compiler handles GNU-style inline assembly.
271 #if (defined _MSC_VER)
274 #if (_MSC_VER > 1500) || (_MSC_VER == 1500 & _MSC_FULL_VER >= 150030729)
275 /* MSVC 9.0 SP1 or later */
276 __cpuidex(CPUInfo, level, ecxval);
279 __cpuid(CPUInfo, level);
280 /* Set an error code if the user wanted a non-zero ecxval, since we did not have cpuidex */
281 rc = (ecxval > 0) ? -1 : 0;
288 #elif (defined GMX_X86_GCC_INLINE_ASM)
289 /* for now this means GMX_X86_GCC_INLINE_ASM should be defined,
290 * but there might be more options added in the future.
296 #if defined(__i386__) && defined(__PIC__)
297 /* Avoid clobbering the global offset table in 32-bit pic code (ebx register) */
298 __asm__ __volatile__ ("xchgl %%ebx, %1 \n\t"
300 "xchgl %%ebx, %1 \n\t"
301 : "+a" (*eax), "+r" (*ebx), "+c" (*ecx), "+d" (*edx));
303 /* i386 without PIC, or x86-64. Things are easy and we can clobber any reg we want :-) */
304 __asm__ __volatile__ ("cpuid \n\t"
305 : "+a" (*eax), "+b" (*ebx), "+c" (*ecx), "+d" (*edx));
310 * Apparently this is an x86 platform where we don't know how to call cpuid.
312 * This is REALLY bad, since we will lose all Gromacs SIMD support.
325 /* Identify CPU features common to Intel & AMD - mainly brand string,
326 * version and some features. Vendor has already been detected outside this.
329 cpuid_check_common_x86(gmx_cpuid_t cpuid)
331 int fn, max_stdfn, max_extfn;
332 unsigned int eax, ebx, ecx, edx;
333 char str[GMX_CPUID_BRAND_MAXLEN];
336 /* Find largest standard/extended function input value */
337 execute_x86cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
339 execute_x86cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
343 if (max_extfn >= 0x80000005)
345 /* Get CPU brand string */
346 for (fn = 0x80000002; fn < 0x80000005; fn++)
348 execute_x86cpuid(fn, 0, &eax, &ebx, &ecx, &edx);
350 memcpy(p+4, &ebx, 4);
351 memcpy(p+8, &ecx, 4);
352 memcpy(p+12, &edx, 4);
357 /* Remove empty initial space */
359 while (isspace(*(p)))
363 strncpy(cpuid->brand, p, GMX_CPUID_BRAND_MAXLEN);
367 strncpy(cpuid->brand, "Unknown CPU brand", GMX_CPUID_BRAND_MAXLEN);
370 /* Find basic CPU properties */
373 execute_x86cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
375 cpuid->family = ((eax & 0x0FF00000) >> 20) + ((eax & 0x00000F00) >> 8);
376 /* Note that extended model should be shifted left 4, so only shift right 12 iso 16. */
377 cpuid->model = ((eax & 0x000F0000) >> 12) + ((eax & 0x000000F0) >> 4);
378 cpuid->stepping = (eax & 0x0000000F);
380 /* Feature flags common to AMD and intel */
381 cpuid->feature[GMX_CPUID_FEATURE_X86_SSE3] = (ecx & (1 << 0)) != 0;
382 cpuid->feature[GMX_CPUID_FEATURE_X86_PCLMULDQ] = (ecx & (1 << 1)) != 0;
383 cpuid->feature[GMX_CPUID_FEATURE_X86_SSSE3] = (ecx & (1 << 9)) != 0;
384 cpuid->feature[GMX_CPUID_FEATURE_X86_FMA] = (ecx & (1 << 12)) != 0;
385 cpuid->feature[GMX_CPUID_FEATURE_X86_CX16] = (ecx & (1 << 13)) != 0;
386 cpuid->feature[GMX_CPUID_FEATURE_X86_SSE4_1] = (ecx & (1 << 19)) != 0;
387 cpuid->feature[GMX_CPUID_FEATURE_X86_SSE4_2] = (ecx & (1 << 20)) != 0;
388 cpuid->feature[GMX_CPUID_FEATURE_X86_POPCNT] = (ecx & (1 << 23)) != 0;
389 cpuid->feature[GMX_CPUID_FEATURE_X86_AES] = (ecx & (1 << 25)) != 0;
390 cpuid->feature[GMX_CPUID_FEATURE_X86_AVX] = (ecx & (1 << 28)) != 0;
391 cpuid->feature[GMX_CPUID_FEATURE_X86_F16C] = (ecx & (1 << 29)) != 0;
392 cpuid->feature[GMX_CPUID_FEATURE_X86_RDRND] = (ecx & (1 << 30)) != 0;
394 cpuid->feature[GMX_CPUID_FEATURE_X86_PSE] = (edx & (1 << 3)) != 0;
395 cpuid->feature[GMX_CPUID_FEATURE_X86_MSR] = (edx & (1 << 5)) != 0;
396 cpuid->feature[GMX_CPUID_FEATURE_X86_CX8] = (edx & (1 << 8)) != 0;
397 cpuid->feature[GMX_CPUID_FEATURE_X86_APIC] = (edx & (1 << 9)) != 0;
398 cpuid->feature[GMX_CPUID_FEATURE_X86_CMOV] = (edx & (1 << 15)) != 0;
399 cpuid->feature[GMX_CPUID_FEATURE_X86_CLFSH] = (edx & (1 << 19)) != 0;
400 cpuid->feature[GMX_CPUID_FEATURE_X86_MMX] = (edx & (1 << 23)) != 0;
401 cpuid->feature[GMX_CPUID_FEATURE_X86_SSE2] = (edx & (1 << 26)) != 0;
402 cpuid->feature[GMX_CPUID_FEATURE_X86_HTT] = (edx & (1 << 28)) != 0;
408 cpuid->stepping = -1;
411 if (max_extfn >= 0x80000001)
413 execute_x86cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
414 cpuid->feature[GMX_CPUID_FEATURE_X86_LAHF_LM] = (ecx & (1 << 0)) != 0;
415 cpuid->feature[GMX_CPUID_FEATURE_X86_PDPE1GB] = (edx & (1 << 26)) != 0;
416 cpuid->feature[GMX_CPUID_FEATURE_X86_RDTSCP] = (edx & (1 << 27)) != 0;
419 if (max_extfn >= 0x80000007)
421 execute_x86cpuid(0x80000007, 0, &eax, &ebx, &ecx, &edx);
422 cpuid->feature[GMX_CPUID_FEATURE_X86_NONSTOP_TSC] = (edx & (1 << 8)) != 0;
427 /* This routine returns the number of unique different elements found in the array,
428 * and renumbers these starting from 0. For example, the array {0,1,2,8,9,10,8,9,10,0,1,2}
429 * will be rewritten to {0,1,2,3,4,5,3,4,5,0,1,2}, and it returns 6 for the
430 * number of unique elements.
433 cpuid_renumber_elements(int *data, int n)
436 int i, j, nunique, found;
438 unique = malloc(sizeof(int)*n);
441 for (i = 0; i < n; i++)
443 for (j = 0, found = 0; j < nunique && !found; j++)
445 found = (data[i] == unique[j]);
449 /* Insert in sorted order! */
450 for (j = nunique++; j > 0 && unique[j-1] > data[i]; j--)
452 unique[j] = unique[j-1];
458 for (i = 0; i < n; i++)
460 for (j = 0; j < nunique; j++)
462 if (data[i] == unique[j])
471 /* APIC IDs, or everything you wanted to know about your x86 cores but were afraid to ask...
473 * Raw APIC IDs are unfortunately somewhat dirty. For technical reasons they are assigned
474 * in power-of-2 chunks, and even then there are no guarantees about specific numbers - all
475 * we know is that the part for each thread/core/package is unique, and how many bits are
476 * reserved for that part.
477 * This routine does internal renumbering so we get continuous indices, and also
478 * decodes the actual number of packages,cores-per-package and hwthreads-per-core.
479 * Returns: 0 on success, non-zero on failure.
482 cpuid_x86_decode_apic_id(gmx_cpuid_t cpuid, int *apic_id, int core_bits, int hwthread_bits)
485 int hwthread_mask, core_mask_after_shift;
487 cpuid->hwthread_id = malloc(sizeof(int)*cpuid->nproc);
488 cpuid->core_id = malloc(sizeof(int)*cpuid->nproc);
489 cpuid->package_id = malloc(sizeof(int)*cpuid->nproc);
490 cpuid->locality_order = malloc(sizeof(int)*cpuid->nproc);
492 hwthread_mask = (1 << hwthread_bits) - 1;
493 core_mask_after_shift = (1 << core_bits) - 1;
495 for (i = 0; i < cpuid->nproc; i++)
497 cpuid->hwthread_id[i] = apic_id[i] & hwthread_mask;
498 cpuid->core_id[i] = (apic_id[i] >> hwthread_bits) & core_mask_after_shift;
499 cpuid->package_id[i] = apic_id[i] >> (core_bits + hwthread_bits);
502 cpuid->npackages = cpuid_renumber_elements(cpuid->package_id, cpuid->nproc);
503 cpuid->ncores_per_package = cpuid_renumber_elements(cpuid->core_id, cpuid->nproc);
504 cpuid->nhwthreads_per_core = cpuid_renumber_elements(cpuid->hwthread_id, cpuid->nproc);
506 /* now check for consistency */
507 if ( (cpuid->npackages * cpuid->ncores_per_package *
508 cpuid->nhwthreads_per_core) != cpuid->nproc)
510 /* the packages/cores-per-package/hwthreads-per-core counts are
515 /* Create a locality order array, i.e. first all resources in package0, which in turn
516 * are sorted so we first have all resources in core0, where threads are sorted in order, etc.
519 for (i = 0; i < cpuid->nproc; i++)
521 idx = (cpuid->package_id[i]*cpuid->ncores_per_package + cpuid->core_id[i])*cpuid->nhwthreads_per_core + cpuid->hwthread_id[i];
522 cpuid->locality_order[idx] = i;
528 /* Detection of AMD-specific CPU features */
530 cpuid_check_amd_x86(gmx_cpuid_t cpuid)
532 int max_stdfn, max_extfn, ret;
533 unsigned int eax, ebx, ecx, edx;
534 int hwthread_bits, core_bits;
537 cpuid_check_common_x86(cpuid);
539 execute_x86cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
542 execute_x86cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
545 if (max_extfn >= 0x80000001)
547 execute_x86cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
549 cpuid->feature[GMX_CPUID_FEATURE_X86_SSE4A] = (ecx & (1 << 6)) != 0;
550 cpuid->feature[GMX_CPUID_FEATURE_X86_MISALIGNSSE] = (ecx & (1 << 7)) != 0;
551 cpuid->feature[GMX_CPUID_FEATURE_X86_XOP] = (ecx & (1 << 11)) != 0;
552 cpuid->feature[GMX_CPUID_FEATURE_X86_FMA4] = (ecx & (1 << 16)) != 0;
555 /* Query APIC information on AMD */
556 if (max_extfn >= 0x80000008)
558 #if (defined HAVE_SCHED_H && defined HAVE_SCHED_SETAFFINITY && defined HAVE_SYSCONF && defined __linux__)
561 cpu_set_t cpuset, save_cpuset;
562 cpuid->nproc = sysconf(_SC_NPROCESSORS_ONLN);
563 apic_id = malloc(sizeof(int)*cpuid->nproc);
564 sched_getaffinity(0, sizeof(cpu_set_t), &save_cpuset);
565 /* Get APIC id from each core */
567 for (i = 0; i < cpuid->nproc; i++)
570 sched_setaffinity(0, sizeof(cpu_set_t), &cpuset);
571 execute_x86cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
572 apic_id[i] = ebx >> 24;
575 /* Reset affinity to the value it had when calling this routine */
576 sched_setaffinity(0, sizeof(cpu_set_t), &save_cpuset);
577 #define CPUID_HAVE_APIC
578 #elif defined GMX_NATIVE_WINDOWS
582 unsigned int save_affinity, affinity;
583 GetSystemInfo( &sysinfo );
584 cpuid->nproc = sysinfo.dwNumberOfProcessors;
585 apic_id = malloc(sizeof(int)*cpuid->nproc);
586 /* Get previous affinity mask */
587 save_affinity = SetThreadAffinityMask(GetCurrentThread(), 1);
588 for (i = 0; i < cpuid->nproc; i++)
590 SetThreadAffinityMask(GetCurrentThread(), (((DWORD_PTR)1)<<i));
592 execute_x86cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
593 apic_id[i] = ebx >> 24;
595 SetThreadAffinityMask(GetCurrentThread(), save_affinity);
596 #define CPUID_HAVE_APIC
598 #ifdef CPUID_HAVE_APIC
599 /* AMD does not support SMT yet - there are no hwthread bits in apic ID */
601 /* Get number of core bits in apic ID - try modern extended method first */
602 execute_x86cpuid(0x80000008, 0, &eax, &ebx, &ecx, &edx);
603 core_bits = (ecx >> 12) & 0xf;
606 /* Legacy method for old single/dual core AMD CPUs */
608 for (core_bits = 0; (i>>core_bits) > 0; core_bits++)
613 ret = cpuid_x86_decode_apic_id(cpuid, apic_id, core_bits,
615 cpuid->have_cpu_topology = (ret == 0);
621 /* Detection of Intel-specific CPU features */
623 cpuid_check_intel_x86(gmx_cpuid_t cpuid)
625 unsigned int max_stdfn, max_extfn, ret;
626 unsigned int eax, ebx, ecx, edx;
627 unsigned int max_logical_cores, max_physical_cores;
628 int hwthread_bits, core_bits;
631 cpuid_check_common_x86(cpuid);
633 execute_x86cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
636 execute_x86cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
641 execute_x86cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
642 cpuid->feature[GMX_CPUID_FEATURE_X86_PDCM] = (ecx & (1 << 15)) != 0;
643 cpuid->feature[GMX_CPUID_FEATURE_X86_PCID] = (ecx & (1 << 17)) != 0;
644 cpuid->feature[GMX_CPUID_FEATURE_X86_X2APIC] = (ecx & (1 << 21)) != 0;
645 cpuid->feature[GMX_CPUID_FEATURE_X86_TDT] = (ecx & (1 << 24)) != 0;
650 execute_x86cpuid(0x7, 0, &eax, &ebx, &ecx, &edx);
651 cpuid->feature[GMX_CPUID_FEATURE_X86_AVX2] = (ebx & (1 << 5)) != 0;
654 /* Check whether Hyper-Threading is enabled, not only supported */
655 if (cpuid->feature[GMX_CPUID_FEATURE_X86_HTT] && max_stdfn >= 4)
657 execute_x86cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
658 max_logical_cores = (ebx >> 16) & 0x0FF;
659 execute_x86cpuid(0x4, 0, &eax, &ebx, &ecx, &edx);
660 max_physical_cores = ((eax >> 26) & 0x3F) + 1;
662 /* Clear HTT flag if we only have 1 logical core per physical */
663 if (max_logical_cores/max_physical_cores < 2)
665 cpuid->feature[GMX_CPUID_FEATURE_X86_HTT] = 0;
669 if (max_stdfn >= 0xB)
671 /* Query x2 APIC information from cores */
672 #if (defined HAVE_SCHED_H && defined HAVE_SCHED_SETAFFINITY && defined HAVE_SYSCONF && defined __linux__)
675 cpu_set_t cpuset, save_cpuset;
676 cpuid->nproc = sysconf(_SC_NPROCESSORS_ONLN);
677 apic_id = malloc(sizeof(int)*cpuid->nproc);
678 sched_getaffinity(0, sizeof(cpu_set_t), &save_cpuset);
679 /* Get x2APIC ID from each hardware thread */
681 for (i = 0; i < cpuid->nproc; i++)
684 sched_setaffinity(0, sizeof(cpu_set_t), &cpuset);
685 execute_x86cpuid(0xB, 0, &eax, &ebx, &ecx, &edx);
689 /* Reset affinity to the value it had when calling this routine */
690 sched_setaffinity(0, sizeof(cpu_set_t), &save_cpuset);
691 #define CPUID_HAVE_APIC
692 #elif defined GMX_NATIVE_WINDOWS
696 unsigned int save_affinity, affinity;
697 GetSystemInfo( &sysinfo );
698 cpuid->nproc = sysinfo.dwNumberOfProcessors;
699 apic_id = malloc(sizeof(int)*cpuid->nproc);
700 /* Get previous affinity mask */
701 save_affinity = SetThreadAffinityMask(GetCurrentThread(), 1);
702 for (i = 0; i < cpuid->nproc; i++)
704 SetThreadAffinityMask(GetCurrentThread(), (((DWORD_PTR)1)<<i));
706 execute_x86cpuid(0xB, 0, &eax, &ebx, &ecx, &edx);
709 SetThreadAffinityMask(GetCurrentThread(), save_affinity);
710 #define CPUID_HAVE_APIC
712 #ifdef CPUID_HAVE_APIC
713 execute_x86cpuid(0xB, 0, &eax, &ebx, &ecx, &edx);
714 hwthread_bits = eax & 0x1F;
715 execute_x86cpuid(0xB, 1, &eax, &ebx, &ecx, &edx);
716 core_bits = (eax & 0x1F) - hwthread_bits;
717 ret = cpuid_x86_decode_apic_id(cpuid, apic_id, core_bits,
719 cpuid->have_cpu_topology = (ret == 0);
724 #endif /* GMX_CPUID_X86 */
730 chomp_substring_before_colon(const char *in, char *s, int maxlength)
733 strncpy(s, in, maxlength);
738 while (isspace(*(--p)) && (p >= s))
750 chomp_substring_after_colon(const char *in, char *s, int maxlength)
753 if ( (p = strchr(in, ':')) != NULL)
760 strncpy(s, p, maxlength);
762 while (isspace(*(--p)) && (p >= s))
773 /* Try to find the vendor of the current CPU, so we know what specific
774 * detection routine to call.
776 static enum gmx_cpuid_vendor
777 cpuid_check_vendor(void)
779 enum gmx_cpuid_vendor i, vendor;
780 /* Register data used on x86 */
781 unsigned int eax, ebx, ecx, edx;
782 char vendorstring[13];
784 char buffer[255], before_colon[255], after_colon[255];
786 /* Set default first */
787 vendor = GMX_CPUID_VENDOR_UNKNOWN;
790 execute_x86cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
792 memcpy(vendorstring, &ebx, 4);
793 memcpy(vendorstring+4, &edx, 4);
794 memcpy(vendorstring+8, &ecx, 4);
796 vendorstring[12] = '\0';
798 for (i = GMX_CPUID_VENDOR_UNKNOWN; i < GMX_CPUID_NVENDORS; i++)
800 if (!strncmp(vendorstring, gmx_cpuid_vendor_string[i], 12))
805 #elif defined(__linux__) || defined(__linux)
806 /* General Linux. Try to get CPU vendor from /proc/cpuinfo */
807 if ( (fp = fopen("/proc/cpuinfo", "r")) != NULL)
809 while ( (vendor == GMX_CPUID_VENDOR_UNKNOWN) && (fgets(buffer, sizeof(buffer), fp) != NULL))
811 chomp_substring_before_colon(buffer, before_colon, sizeof(before_colon));
812 /* Intel/AMD use "vendor_id", IBM "vendor"(?) or "model". Fujitsu "manufacture". Add others if you have them! */
813 if (!strcmp(before_colon, "vendor_id")
814 || !strcmp(before_colon, "vendor")
815 || !strcmp(before_colon, "manufacture")
816 || !strcmp(before_colon, "model"))
818 chomp_substring_after_colon(buffer, after_colon, sizeof(after_colon));
819 for (i = GMX_CPUID_VENDOR_UNKNOWN; i < GMX_CPUID_NVENDORS; i++)
821 /* Be liberal and accept if we find the vendor
822 * string (or alternative string) anywhere. Using
823 * strcasestr() would be non-portable. */
824 if (strstr(after_colon, gmx_cpuid_vendor_string[i])
825 || strstr(after_colon, gmx_cpuid_vendor_string_alternative[i]))
842 gmx_cpuid_topology(gmx_cpuid_t cpuid,
845 int * ncores_per_package,
846 int * nhwthreads_per_core,
847 const int ** package_id,
848 const int ** core_id,
849 const int ** hwthread_id,
850 const int ** locality_order)
854 if (cpuid->have_cpu_topology)
856 *nprocessors = cpuid->nproc;
857 *npackages = cpuid->npackages;
858 *ncores_per_package = cpuid->ncores_per_package;
859 *nhwthreads_per_core = cpuid->nhwthreads_per_core;
860 *package_id = cpuid->package_id;
861 *core_id = cpuid->core_id;
862 *hwthread_id = cpuid->hwthread_id;
863 *locality_order = cpuid->locality_order;
874 enum gmx_cpuid_x86_smt
875 gmx_cpuid_x86_smt(gmx_cpuid_t cpuid)
877 enum gmx_cpuid_x86_smt rc;
879 if (cpuid->have_cpu_topology)
881 rc = (cpuid->nhwthreads_per_core > 1) ? GMX_CPUID_X86_SMT_ENABLED : GMX_CPUID_X86_SMT_DISABLED;
883 else if (cpuid->vendor == GMX_CPUID_VENDOR_AMD || gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_HTT) == 0)
885 rc = GMX_CPUID_X86_SMT_DISABLED;
889 rc = GMX_CPUID_X86_SMT_CANNOTDETECT;
896 gmx_cpuid_init (gmx_cpuid_t * pcpuid)
901 char buffer[255], buffer2[255];
904 cpuid = malloc(sizeof(*cpuid));
908 for (i = 0; i < GMX_CPUID_NFEATURES; i++)
910 cpuid->feature[i] = 0;
913 cpuid->have_cpu_topology = 0;
915 cpuid->npackages = 0;
916 cpuid->ncores_per_package = 0;
917 cpuid->nhwthreads_per_core = 0;
918 cpuid->package_id = NULL;
919 cpuid->core_id = NULL;
920 cpuid->hwthread_id = NULL;
921 cpuid->locality_order = NULL;
923 cpuid->vendor = cpuid_check_vendor();
925 switch (cpuid->vendor)
928 case GMX_CPUID_VENDOR_INTEL:
929 cpuid_check_intel_x86(cpuid);
931 case GMX_CPUID_VENDOR_AMD:
932 cpuid_check_amd_x86(cpuid);
937 strncpy(cpuid->brand, "Unknown CPU brand", GMX_CPUID_BRAND_MAXLEN);
938 #if defined(__linux__) || defined(__linux)
939 /* General Linux. Try to get CPU type from /proc/cpuinfo */
940 if ( (fp = fopen("/proc/cpuinfo", "r")) != NULL)
943 while ( (found_brand == 0) && (fgets(buffer, sizeof(buffer), fp) != NULL))
945 chomp_substring_before_colon(buffer, buffer2, sizeof(buffer2));
946 /* Intel uses "model name", Fujitsu and IBM "cpu". */
947 if (!strcmp(buffer2, "model name") || !strcmp(buffer2, "cpu"))
949 chomp_substring_after_colon(buffer, cpuid->brand, GMX_CPUID_BRAND_MAXLEN);
960 for (i = 0; i < GMX_CPUID_NFEATURES; i++)
962 cpuid->feature[i] = 0;
964 cpuid->feature[GMX_CPUID_FEATURE_CANNOTDETECT] = 1;
973 gmx_cpuid_done (gmx_cpuid_t cpuid)
980 gmx_cpuid_formatstring (gmx_cpuid_t cpuid,
986 enum gmx_cpuid_feature feature;
992 "Family: %2d Model: %2d Stepping: %2d\n"
994 gmx_cpuid_vendor_string[gmx_cpuid_vendor(cpuid)],
995 gmx_cpuid_brand(cpuid),
996 gmx_cpuid_family(cpuid), gmx_cpuid_model(cpuid), gmx_cpuid_stepping(cpuid));
1001 "Family: %2d Model: %2d Stepping: %2d\n"
1003 gmx_cpuid_vendor_string[gmx_cpuid_vendor(cpuid)],
1004 gmx_cpuid_brand(cpuid),
1005 gmx_cpuid_family(cpuid), gmx_cpuid_model(cpuid), gmx_cpuid_stepping(cpuid));
1013 for (feature = GMX_CPUID_FEATURE_CANNOTDETECT; feature < GMX_CPUID_NFEATURES; feature++)
1015 if (gmx_cpuid_feature(cpuid, feature) == 1)
1018 _snprintf(str, n, " %s", gmx_cpuid_feature_string[feature]);
1020 snprintf(str, n, " %s", gmx_cpuid_feature_string[feature]);
1029 _snprintf(str, n, "\n");
1031 snprintf(str, n, "\n");
1041 gmx_cpuid_simd_suggest (gmx_cpuid_t cpuid)
1043 enum gmx_cpuid_simd tmpsimd;
1045 tmpsimd = GMX_CPUID_SIMD_NONE;
1047 if (gmx_cpuid_vendor(cpuid) == GMX_CPUID_VENDOR_INTEL)
1049 if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_AVX2))
1051 tmpsimd = GMX_CPUID_SIMD_X86_AVX2_256;
1053 else if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_AVX))
1055 tmpsimd = GMX_CPUID_SIMD_X86_AVX_256;
1057 else if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_SSE4_1))
1059 tmpsimd = GMX_CPUID_SIMD_X86_SSE4_1;
1061 else if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_SSE2))
1063 tmpsimd = GMX_CPUID_SIMD_X86_SSE2;
1066 else if (gmx_cpuid_vendor(cpuid) == GMX_CPUID_VENDOR_AMD)
1068 if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_AVX))
1070 tmpsimd = GMX_CPUID_SIMD_X86_AVX_128_FMA;
1072 else if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_SSE4_1))
1074 tmpsimd = GMX_CPUID_SIMD_X86_SSE4_1;
1076 else if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_SSE2))
1078 tmpsimd = GMX_CPUID_SIMD_X86_SSE2;
1081 else if (gmx_cpuid_vendor(cpuid) == GMX_CPUID_VENDOR_FUJITSU)
1083 if (strstr(gmx_cpuid_brand(cpuid), "SPARC64"))
1085 tmpsimd = GMX_CPUID_SIMD_SPARC64_HPC_ACE;
1088 else if (gmx_cpuid_vendor(cpuid) == GMX_CPUID_VENDOR_IBM)
1090 if (strstr(gmx_cpuid_brand(cpuid), "A2"))
1092 tmpsimd = GMX_CPUID_SIMD_IBM_QPX;
1101 gmx_cpuid_simd_check(gmx_cpuid_t cpuid,
1103 int print_to_stderr)
1107 enum gmx_cpuid_simd simd;
1109 simd = gmx_cpuid_simd_suggest(cpuid);
1111 rc = (simd != compiled_simd);
1113 gmx_cpuid_formatstring(cpuid, str, 1023);
1119 "\nDetecting CPU SIMD instructions.\nPresent hardware specification:\n"
1121 "SIMD instructions most likely to fit this hardware: %s\n"
1122 "SIMD instructions selected at GROMACS compile time: %s\n\n",
1124 gmx_cpuid_simd_string[simd],
1125 gmx_cpuid_simd_string[compiled_simd]);
1132 fprintf(log, "\nBinary not matching hardware - you might be losing performance.\n"
1133 "SIMD instructions most likely to fit this hardware: %s\n"
1134 "SIMD instructions selected at GROMACS compile time: %s\n\n",
1135 gmx_cpuid_simd_string[simd],
1136 gmx_cpuid_simd_string[compiled_simd]);
1138 if (print_to_stderr)
1140 fprintf(stderr, "Compiled SIMD instructions: %s (Gromacs could use %s on this machine, which is better)\n",
1141 gmx_cpuid_simd_string[compiled_simd],
1142 gmx_cpuid_simd_string[simd]);
1149 #ifdef GMX_CPUID_STANDALONE
1150 /* Stand-alone program to enable queries of CPU features from Cmake.
1151 * Note that you need to check inline ASM capabilities before compiling and set
1152 * -DGMX_X86_GCC_INLINE_ASM for the cpuid instruction to work...
1155 main(int argc, char **argv)
1158 enum gmx_cpuid_simd simd;
1164 "Usage:\n\n%s [flags]\n\n"
1165 "Available flags:\n"
1166 "-vendor Print CPU vendor.\n"
1167 "-brand Print CPU brand string.\n"
1168 "-family Print CPU family version.\n"
1169 "-model Print CPU model version.\n"
1170 "-stepping Print CPU stepping version.\n"
1171 "-features Print CPU feature flags.\n"
1172 "-simd Print suggested GROMACS SIMD instructions.\n",
1177 gmx_cpuid_init(&cpuid);
1179 if (!strncmp(argv[1], "-vendor", 3))
1181 printf("%s\n", gmx_cpuid_vendor_string[cpuid->vendor]);
1183 else if (!strncmp(argv[1], "-brand", 3))
1185 printf("%s\n", cpuid->brand);
1187 else if (!strncmp(argv[1], "-family", 3))
1189 printf("%d\n", cpuid->family);
1191 else if (!strncmp(argv[1], "-model", 3))
1193 printf("%d\n", cpuid->model);
1195 else if (!strncmp(argv[1], "-stepping", 3))
1197 printf("%d\n", cpuid->stepping);
1199 else if (!strncmp(argv[1], "-features", 3))
1202 for (i = 0; i < GMX_CPUID_NFEATURES; i++)
1204 if (cpuid->feature[i] == 1)
1210 printf("%s", gmx_cpuid_feature_string[i]);
1215 else if (!strncmp(argv[1], "-simd", 3))
1217 simd = gmx_cpuid_simd_suggest(cpuid);
1218 fprintf(stdout, "%s\n", gmx_cpuid_simd_string[simd]);
1221 gmx_cpuid_done(cpuid);