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49 /* MSVC definition for __cpuid() */
51 /* sysinfo functions */
55 /* sysconf() definition */
59 #include "gmx_cpuid.h"
63 /* For convenience, and to enable configure-time invocation, we keep all architectures
64 * in a single file, but to avoid repeated ifdefs we set the overall architecture here.
67 /* OK, it is x86, but can we execute cpuid? */
68 #if defined(GMX_X86_GCC_INLINE_ASM) || ( defined(_MSC_VER) && ( (_MSC_VER > 1500) || (_MSC_VER == 1500 & _MSC_FULL_VER >= 150030729)))
69 # define GMX_CPUID_X86
73 /* Global constant character strings corresponding to our enumerated types */
75 gmx_cpuid_vendor_string[GMX_CPUID_NVENDORS] =
86 gmx_cpuid_vendor_string_alternative[GMX_CPUID_NVENDORS] =
93 "ibm" /* Used on BlueGene/Q */
97 gmx_cpuid_feature_string[GMX_CPUID_NFEATURES] =
137 gmx_cpuid_simd_string[GMX_CPUID_NSIMD] =
150 /* Max length of brand string */
151 #define GMX_CPUID_BRAND_MAXLEN 256
154 /* Contents of the abstract datatype */
157 enum gmx_cpuid_vendor vendor;
158 char brand[GMX_CPUID_BRAND_MAXLEN];
162 /* Not using gmx_bool here, since this file must be possible to compile without simple.h */
163 char feature[GMX_CPUID_NFEATURES];
165 /* Basic CPU topology information. For x86 this is a bit complicated since the topology differs between
166 * operating systems and sometimes even settings. For most other architectures you can likely just check
167 * the documentation and then write static information to these arrays rather than detecting on-the-fly.
169 int have_cpu_topology;
170 int nproc; /* total number of logical processors from OS */
172 int ncores_per_package;
173 int nhwthreads_per_core;
175 int * core_id; /* Local core id in each package */
176 int * hwthread_id; /* Local hwthread id in each core */
177 int * locality_order; /* Processor indices sorted in locality order */
181 /* Simple routines to access the data structure. The initialization routine is
182 * further down since that needs to call other static routines in this file.
184 enum gmx_cpuid_vendor
185 gmx_cpuid_vendor (gmx_cpuid_t cpuid)
187 return cpuid->vendor;
192 gmx_cpuid_brand (gmx_cpuid_t cpuid)
198 gmx_cpuid_family (gmx_cpuid_t cpuid)
200 return cpuid->family;
204 gmx_cpuid_model (gmx_cpuid_t cpuid)
210 gmx_cpuid_stepping (gmx_cpuid_t cpuid)
212 return cpuid->stepping;
216 gmx_cpuid_feature (gmx_cpuid_t cpuid,
217 enum gmx_cpuid_feature feature)
219 return (cpuid->feature[feature] != 0);
225 /* What type of SIMD was compiled in, if any?
226 * This is set from Cmake. Note that the SSE2 and SSE4_1 macros are set for
227 * AVX too, so it is important that they appear last in the list.
229 #ifdef GMX_SIMD_X86_AVX_256
230 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_X86_AVX_256;
231 #elif defined GMX_SIMD_X86_AVX_128_FMA
232 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_X86_AVX_128_FMA;
233 #elif defined GMX_SIMD_X86_SSE4_1
234 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_X86_SSE4_1;
235 #elif defined GMX_SIMD_X86_SSE2
236 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_X86_SSE2;
237 #elif defined GMX_SIMD_SPARC64_HPC_ACE
238 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_SPARC64_HPC_ACE;
239 #elif defined GMX_SIMD_IBM_QPX
240 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_IBM_QPX;
242 static const enum gmx_cpuid_simd compiled_simd = GMX_CPUID_SIMD_NONE;
248 /* Execute CPUID on x86 class CPUs. level sets function to exec, and the
249 * contents of register output is returned. See Intel/AMD docs for details.
251 * This version supports extended information where we can also have an input
252 * value in the ecx register. This is ignored for most levels, but some of them
253 * (e.g. level 0xB on Intel) use it.
256 execute_x86cpuid(unsigned int level,
265 /* Currently CPUID is only supported (1) if we can use an instruction on MSVC, or (2)
266 * if the compiler handles GNU-style inline assembly.
269 #if (defined _MSC_VER)
272 #if (_MSC_VER > 1500) || (_MSC_VER == 1500 & _MSC_FULL_VER >= 150030729)
273 /* MSVC 9.0 SP1 or later */
274 __cpuidex(CPUInfo, level, ecxval);
277 __cpuid(CPUInfo, level);
278 /* Set an error code if the user wanted a non-zero ecxval, since we did not have cpuidex */
279 rc = (ecxval > 0) ? -1 : 0;
286 #elif (defined GMX_X86_GCC_INLINE_ASM)
287 /* for now this means GMX_X86_GCC_INLINE_ASM should be defined,
288 * but there might be more options added in the future.
294 #if defined(__i386__) && defined(__PIC__)
295 /* Avoid clobbering the global offset table in 32-bit pic code (ebx register) */
296 __asm__ __volatile__ ("xchgl %%ebx, %1 \n\t"
298 "xchgl %%ebx, %1 \n\t"
299 : "+a" (*eax), "+r" (*ebx), "+c" (*ecx), "+d" (*edx));
301 /* i386 without PIC, or x86-64. Things are easy and we can clobber any reg we want :-) */
302 __asm__ __volatile__ ("cpuid \n\t"
303 : "+a" (*eax), "+b" (*ebx), "+c" (*ecx), "+d" (*edx));
308 * Apparently this is an x86 platform where we don't know how to call cpuid.
310 * This is REALLY bad, since we will lose all Gromacs SIMD support.
323 /* Identify CPU features common to Intel & AMD - mainly brand string,
324 * version and some features. Vendor has already been detected outside this.
327 cpuid_check_common_x86(gmx_cpuid_t cpuid)
329 int fn, max_stdfn, max_extfn;
330 unsigned int eax, ebx, ecx, edx;
331 char str[GMX_CPUID_BRAND_MAXLEN];
334 /* Find largest standard/extended function input value */
335 execute_x86cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
337 execute_x86cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
341 if (max_extfn >= 0x80000005)
343 /* Get CPU brand string */
344 for (fn = 0x80000002; fn < 0x80000005; fn++)
346 execute_x86cpuid(fn, 0, &eax, &ebx, &ecx, &edx);
348 memcpy(p+4, &ebx, 4);
349 memcpy(p+8, &ecx, 4);
350 memcpy(p+12, &edx, 4);
355 /* Remove empty initial space */
357 while (isspace(*(p)))
361 strncpy(cpuid->brand, p, GMX_CPUID_BRAND_MAXLEN);
365 strncpy(cpuid->brand, "Unknown CPU brand", GMX_CPUID_BRAND_MAXLEN);
368 /* Find basic CPU properties */
371 execute_x86cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
373 cpuid->family = ((eax & 0x0FF00000) >> 20) + ((eax & 0x00000F00) >> 8);
374 /* Note that extended model should be shifted left 4, so only shift right 12 iso 16. */
375 cpuid->model = ((eax & 0x000F0000) >> 12) + ((eax & 0x000000F0) >> 4);
376 cpuid->stepping = (eax & 0x0000000F);
378 /* Feature flags common to AMD and intel */
379 cpuid->feature[GMX_CPUID_FEATURE_X86_SSE3] = (ecx & (1 << 0)) != 0;
380 cpuid->feature[GMX_CPUID_FEATURE_X86_PCLMULDQ] = (ecx & (1 << 1)) != 0;
381 cpuid->feature[GMX_CPUID_FEATURE_X86_SSSE3] = (ecx & (1 << 9)) != 0;
382 cpuid->feature[GMX_CPUID_FEATURE_X86_FMA] = (ecx & (1 << 12)) != 0;
383 cpuid->feature[GMX_CPUID_FEATURE_X86_CX16] = (ecx & (1 << 13)) != 0;
384 cpuid->feature[GMX_CPUID_FEATURE_X86_SSE4_1] = (ecx & (1 << 19)) != 0;
385 cpuid->feature[GMX_CPUID_FEATURE_X86_SSE4_2] = (ecx & (1 << 20)) != 0;
386 cpuid->feature[GMX_CPUID_FEATURE_X86_POPCNT] = (ecx & (1 << 23)) != 0;
387 cpuid->feature[GMX_CPUID_FEATURE_X86_AES] = (ecx & (1 << 25)) != 0;
388 cpuid->feature[GMX_CPUID_FEATURE_X86_AVX] = (ecx & (1 << 28)) != 0;
389 cpuid->feature[GMX_CPUID_FEATURE_X86_F16C] = (ecx & (1 << 29)) != 0;
390 cpuid->feature[GMX_CPUID_FEATURE_X86_RDRND] = (ecx & (1 << 30)) != 0;
392 cpuid->feature[GMX_CPUID_FEATURE_X86_PSE] = (edx & (1 << 3)) != 0;
393 cpuid->feature[GMX_CPUID_FEATURE_X86_MSR] = (edx & (1 << 5)) != 0;
394 cpuid->feature[GMX_CPUID_FEATURE_X86_CX8] = (edx & (1 << 8)) != 0;
395 cpuid->feature[GMX_CPUID_FEATURE_X86_APIC] = (edx & (1 << 9)) != 0;
396 cpuid->feature[GMX_CPUID_FEATURE_X86_CMOV] = (edx & (1 << 15)) != 0;
397 cpuid->feature[GMX_CPUID_FEATURE_X86_CLFSH] = (edx & (1 << 19)) != 0;
398 cpuid->feature[GMX_CPUID_FEATURE_X86_MMX] = (edx & (1 << 23)) != 0;
399 cpuid->feature[GMX_CPUID_FEATURE_X86_SSE2] = (edx & (1 << 26)) != 0;
400 cpuid->feature[GMX_CPUID_FEATURE_X86_HTT] = (edx & (1 << 28)) != 0;
406 cpuid->stepping = -1;
409 if (max_extfn >= 0x80000001)
411 execute_x86cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
412 cpuid->feature[GMX_CPUID_FEATURE_X86_LAHF_LM] = (ecx & (1 << 0)) != 0;
413 cpuid->feature[GMX_CPUID_FEATURE_X86_PDPE1GB] = (edx & (1 << 26)) != 0;
414 cpuid->feature[GMX_CPUID_FEATURE_X86_RDTSCP] = (edx & (1 << 27)) != 0;
417 if (max_extfn >= 0x80000007)
419 execute_x86cpuid(0x80000007, 0, &eax, &ebx, &ecx, &edx);
420 cpuid->feature[GMX_CPUID_FEATURE_X86_NONSTOP_TSC] = (edx & (1 << 8)) != 0;
425 /* This routine returns the number of unique different elements found in the array,
426 * and renumbers these starting from 0. For example, the array {0,1,2,8,9,10,8,9,10,0,1,2}
427 * will be rewritten to {0,1,2,3,4,5,3,4,5,0,1,2}, and it returns 6 for the
428 * number of unique elements.
431 cpuid_renumber_elements(int *data, int n)
434 int i, j, nunique, found;
436 unique = malloc(sizeof(int)*n);
439 for (i = 0; i < n; i++)
441 for (j = 0, found = 0; j < nunique && !found; j++)
443 found = (data[i] == unique[j]);
447 /* Insert in sorted order! */
448 for (j = nunique++; j > 0 && unique[j-1] > data[i]; j--)
450 unique[j] = unique[j-1];
456 for (i = 0; i < n; i++)
458 for (j = 0; j < nunique; j++)
460 if (data[i] == unique[j])
469 /* APIC IDs, or everything you wanted to know about your x86 cores but were afraid to ask...
471 * Raw APIC IDs are unfortunately somewhat dirty. For technical reasons they are assigned
472 * in power-of-2 chunks, and even then there are no guarantees about specific numbers - all
473 * we know is that the part for each thread/core/package is unique, and how many bits are
474 * reserved for that part.
475 * This routine does internal renumbering so we get continuous indices, and also
476 * decodes the actual number of packages,cores-per-package and hwthreads-per-core.
477 * Returns: 0 on success, non-zero on failure.
480 cpuid_x86_decode_apic_id(gmx_cpuid_t cpuid, int *apic_id, int core_bits, int hwthread_bits)
483 int hwthread_mask, core_mask_after_shift;
485 cpuid->hwthread_id = malloc(sizeof(int)*cpuid->nproc);
486 cpuid->core_id = malloc(sizeof(int)*cpuid->nproc);
487 cpuid->package_id = malloc(sizeof(int)*cpuid->nproc);
488 cpuid->locality_order = malloc(sizeof(int)*cpuid->nproc);
490 hwthread_mask = (1 << hwthread_bits) - 1;
491 core_mask_after_shift = (1 << core_bits) - 1;
493 for (i = 0; i < cpuid->nproc; i++)
495 cpuid->hwthread_id[i] = apic_id[i] & hwthread_mask;
496 cpuid->core_id[i] = (apic_id[i] >> hwthread_bits) & core_mask_after_shift;
497 cpuid->package_id[i] = apic_id[i] >> (core_bits + hwthread_bits);
500 cpuid->npackages = cpuid_renumber_elements(cpuid->package_id, cpuid->nproc);
501 cpuid->ncores_per_package = cpuid_renumber_elements(cpuid->core_id, cpuid->nproc);
502 cpuid->nhwthreads_per_core = cpuid_renumber_elements(cpuid->hwthread_id, cpuid->nproc);
504 /* now check for consistency */
505 if ( (cpuid->npackages * cpuid->ncores_per_package *
506 cpuid->nhwthreads_per_core) != cpuid->nproc)
508 /* the packages/cores-per-package/hwthreads-per-core counts are
513 /* Create a locality order array, i.e. first all resources in package0, which in turn
514 * are sorted so we first have all resources in core0, where threads are sorted in order, etc.
517 for (i = 0; i < cpuid->nproc; i++)
519 idx = (cpuid->package_id[i]*cpuid->ncores_per_package + cpuid->core_id[i])*cpuid->nhwthreads_per_core + cpuid->hwthread_id[i];
520 cpuid->locality_order[idx] = i;
526 /* Detection of AMD-specific CPU features */
528 cpuid_check_amd_x86(gmx_cpuid_t cpuid)
530 int max_stdfn, max_extfn, ret;
531 unsigned int eax, ebx, ecx, edx;
532 int hwthread_bits, core_bits;
535 cpuid_check_common_x86(cpuid);
537 execute_x86cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
540 execute_x86cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
543 if (max_extfn >= 0x80000001)
545 execute_x86cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
547 cpuid->feature[GMX_CPUID_FEATURE_X86_SSE4A] = (ecx & (1 << 6)) != 0;
548 cpuid->feature[GMX_CPUID_FEATURE_X86_MISALIGNSSE] = (ecx & (1 << 7)) != 0;
549 cpuid->feature[GMX_CPUID_FEATURE_X86_XOP] = (ecx & (1 << 11)) != 0;
550 cpuid->feature[GMX_CPUID_FEATURE_X86_FMA4] = (ecx & (1 << 16)) != 0;
553 /* Query APIC information on AMD */
554 if (max_extfn >= 0x80000008)
556 #if (defined HAVE_SCHED_H && defined HAVE_SCHED_SETAFFINITY && defined HAVE_SYSCONF && defined __linux__)
559 cpu_set_t cpuset, save_cpuset;
560 cpuid->nproc = sysconf(_SC_NPROCESSORS_ONLN);
561 apic_id = malloc(sizeof(int)*cpuid->nproc);
562 sched_getaffinity(0, sizeof(cpu_set_t), &save_cpuset);
563 /* Get APIC id from each core */
565 for (i = 0; i < cpuid->nproc; i++)
568 sched_setaffinity(0, sizeof(cpu_set_t), &cpuset);
569 execute_x86cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
570 apic_id[i] = ebx >> 24;
573 /* Reset affinity to the value it had when calling this routine */
574 sched_setaffinity(0, sizeof(cpu_set_t), &save_cpuset);
575 #define CPUID_HAVE_APIC
576 #elif defined GMX_NATIVE_WINDOWS
580 unsigned int save_affinity, affinity;
581 GetSystemInfo( &sysinfo );
582 cpuid->nproc = sysinfo.dwNumberOfProcessors;
583 apic_id = malloc(sizeof(int)*cpuid->nproc);
584 /* Get previous affinity mask */
585 save_affinity = SetThreadAffinityMask(GetCurrentThread(), 1);
586 for (i = 0; i < cpuid->nproc; i++)
588 SetThreadAffinityMask(GetCurrentThread(), (((DWORD_PTR)1)<<i));
590 execute_x86cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
591 apic_id[i] = ebx >> 24;
593 SetThreadAffinityMask(GetCurrentThread(), save_affinity);
594 #define CPUID_HAVE_APIC
596 #ifdef CPUID_HAVE_APIC
597 /* AMD does not support SMT yet - there are no hwthread bits in apic ID */
599 /* Get number of core bits in apic ID - try modern extended method first */
600 execute_x86cpuid(0x80000008, 0, &eax, &ebx, &ecx, &edx);
601 core_bits = (ecx >> 12) & 0xf;
604 /* Legacy method for old single/dual core AMD CPUs */
606 for (core_bits = 0; (i>>core_bits) > 0; core_bits++)
611 ret = cpuid_x86_decode_apic_id(cpuid, apic_id, core_bits,
613 cpuid->have_cpu_topology = (ret == 0);
619 /* Detection of Intel-specific CPU features */
621 cpuid_check_intel_x86(gmx_cpuid_t cpuid)
623 unsigned int max_stdfn, max_extfn, ret;
624 unsigned int eax, ebx, ecx, edx;
625 unsigned int max_logical_cores, max_physical_cores;
626 int hwthread_bits, core_bits;
629 cpuid_check_common_x86(cpuid);
631 execute_x86cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
634 execute_x86cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
639 execute_x86cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
640 cpuid->feature[GMX_CPUID_FEATURE_X86_PDCM] = (ecx & (1 << 15)) != 0;
641 cpuid->feature[GMX_CPUID_FEATURE_X86_PCID] = (ecx & (1 << 17)) != 0;
642 cpuid->feature[GMX_CPUID_FEATURE_X86_X2APIC] = (ecx & (1 << 21)) != 0;
643 cpuid->feature[GMX_CPUID_FEATURE_X86_TDT] = (ecx & (1 << 24)) != 0;
648 execute_x86cpuid(0x7, 0, &eax, &ebx, &ecx, &edx);
649 cpuid->feature[GMX_CPUID_FEATURE_X86_AVX2] = (ebx & (1 << 5)) != 0;
652 /* Check whether Hyper-Threading is enabled, not only supported */
653 if (cpuid->feature[GMX_CPUID_FEATURE_X86_HTT] && max_stdfn >= 4)
655 execute_x86cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
656 max_logical_cores = (ebx >> 16) & 0x0FF;
657 execute_x86cpuid(0x4, 0, &eax, &ebx, &ecx, &edx);
658 max_physical_cores = ((eax >> 26) & 0x3F) + 1;
660 /* Clear HTT flag if we only have 1 logical core per physical */
661 if (max_logical_cores/max_physical_cores < 2)
663 cpuid->feature[GMX_CPUID_FEATURE_X86_HTT] = 0;
667 if (max_stdfn >= 0xB)
669 /* Query x2 APIC information from cores */
670 #if (defined HAVE_SCHED_H && defined HAVE_SCHED_SETAFFINITY && defined HAVE_SYSCONF && defined __linux__)
673 cpu_set_t cpuset, save_cpuset;
674 cpuid->nproc = sysconf(_SC_NPROCESSORS_ONLN);
675 apic_id = malloc(sizeof(int)*cpuid->nproc);
676 sched_getaffinity(0, sizeof(cpu_set_t), &save_cpuset);
677 /* Get x2APIC ID from each hardware thread */
679 for (i = 0; i < cpuid->nproc; i++)
682 sched_setaffinity(0, sizeof(cpu_set_t), &cpuset);
683 execute_x86cpuid(0xB, 0, &eax, &ebx, &ecx, &edx);
687 /* Reset affinity to the value it had when calling this routine */
688 sched_setaffinity(0, sizeof(cpu_set_t), &save_cpuset);
689 #define CPUID_HAVE_APIC
690 #elif defined GMX_NATIVE_WINDOWS
694 unsigned int save_affinity, affinity;
695 GetSystemInfo( &sysinfo );
696 cpuid->nproc = sysinfo.dwNumberOfProcessors;
697 apic_id = malloc(sizeof(int)*cpuid->nproc);
698 /* Get previous affinity mask */
699 save_affinity = SetThreadAffinityMask(GetCurrentThread(), 1);
700 for (i = 0; i < cpuid->nproc; i++)
702 SetThreadAffinityMask(GetCurrentThread(), (((DWORD_PTR)1)<<i));
704 execute_x86cpuid(0xB, 0, &eax, &ebx, &ecx, &edx);
707 SetThreadAffinityMask(GetCurrentThread(), save_affinity);
708 #define CPUID_HAVE_APIC
710 #ifdef CPUID_HAVE_APIC
711 execute_x86cpuid(0xB, 0, &eax, &ebx, &ecx, &edx);
712 hwthread_bits = eax & 0x1F;
713 execute_x86cpuid(0xB, 1, &eax, &ebx, &ecx, &edx);
714 core_bits = (eax & 0x1F) - hwthread_bits;
715 ret = cpuid_x86_decode_apic_id(cpuid, apic_id, core_bits,
717 cpuid->have_cpu_topology = (ret == 0);
722 #endif /* GMX_CPUID_X86 */
728 chomp_substring_before_colon(const char *in, char *s, int maxlength)
731 strncpy(s, in, maxlength);
736 while (isspace(*(--p)) && (p >= s))
748 chomp_substring_after_colon(const char *in, char *s, int maxlength)
751 if ( (p = strchr(in, ':')) != NULL)
758 strncpy(s, p, maxlength);
760 while (isspace(*(--p)) && (p >= s))
771 /* Try to find the vendor of the current CPU, so we know what specific
772 * detection routine to call.
774 static enum gmx_cpuid_vendor
775 cpuid_check_vendor(void)
777 enum gmx_cpuid_vendor i, vendor;
778 /* Register data used on x86 */
779 unsigned int eax, ebx, ecx, edx;
780 char vendorstring[13];
782 char buffer[255], before_colon[255], after_colon[255];
784 /* Set default first */
785 vendor = GMX_CPUID_VENDOR_UNKNOWN;
788 execute_x86cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
790 memcpy(vendorstring, &ebx, 4);
791 memcpy(vendorstring+4, &edx, 4);
792 memcpy(vendorstring+8, &ecx, 4);
794 vendorstring[12] = '\0';
796 for (i = GMX_CPUID_VENDOR_UNKNOWN; i < GMX_CPUID_NVENDORS; i++)
798 if (!strncmp(vendorstring, gmx_cpuid_vendor_string[i], 12))
803 #elif defined(__linux__) || defined(__linux)
804 /* General Linux. Try to get CPU vendor from /proc/cpuinfo */
805 if ( (fp = fopen("/proc/cpuinfo", "r")) != NULL)
807 while ( (vendor == GMX_CPUID_VENDOR_UNKNOWN) && (fgets(buffer, sizeof(buffer), fp) != NULL))
809 chomp_substring_before_colon(buffer, before_colon, sizeof(before_colon));
810 /* Intel/AMD use "vendor_id", IBM "vendor"(?) or "model". Fujitsu "manufacture". Add others if you have them! */
811 if (!strcmp(before_colon, "vendor_id")
812 || !strcmp(before_colon, "vendor")
813 || !strcmp(before_colon, "manufacture")
814 || !strcmp(before_colon, "model"))
816 chomp_substring_after_colon(buffer, after_colon, sizeof(after_colon));
817 for (i = GMX_CPUID_VENDOR_UNKNOWN; i < GMX_CPUID_NVENDORS; i++)
819 /* Be liberal and accept if we find the vendor
820 * string (or alternative string) anywhere. Using
821 * strcasestr() would be non-portable. */
822 if (strstr(after_colon, gmx_cpuid_vendor_string[i])
823 || strstr(after_colon, gmx_cpuid_vendor_string_alternative[i]))
840 gmx_cpuid_topology(gmx_cpuid_t cpuid,
843 int * ncores_per_package,
844 int * nhwthreads_per_core,
845 const int ** package_id,
846 const int ** core_id,
847 const int ** hwthread_id,
848 const int ** locality_order)
852 if (cpuid->have_cpu_topology)
854 *nprocessors = cpuid->nproc;
855 *npackages = cpuid->npackages;
856 *ncores_per_package = cpuid->ncores_per_package;
857 *nhwthreads_per_core = cpuid->nhwthreads_per_core;
858 *package_id = cpuid->package_id;
859 *core_id = cpuid->core_id;
860 *hwthread_id = cpuid->hwthread_id;
861 *locality_order = cpuid->locality_order;
872 enum gmx_cpuid_x86_smt
873 gmx_cpuid_x86_smt(gmx_cpuid_t cpuid)
875 enum gmx_cpuid_x86_smt rc;
877 if (cpuid->have_cpu_topology)
879 rc = (cpuid->nhwthreads_per_core > 1) ? GMX_CPUID_X86_SMT_ENABLED : GMX_CPUID_X86_SMT_DISABLED;
881 else if (cpuid->vendor == GMX_CPUID_VENDOR_AMD || gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_HTT) == 0)
883 rc = GMX_CPUID_X86_SMT_DISABLED;
887 rc = GMX_CPUID_X86_SMT_CANNOTDETECT;
894 gmx_cpuid_init (gmx_cpuid_t * pcpuid)
899 char buffer[255], buffer2[255];
902 cpuid = malloc(sizeof(*cpuid));
906 for (i = 0; i < GMX_CPUID_NFEATURES; i++)
908 cpuid->feature[i] = 0;
911 cpuid->have_cpu_topology = 0;
913 cpuid->npackages = 0;
914 cpuid->ncores_per_package = 0;
915 cpuid->nhwthreads_per_core = 0;
916 cpuid->package_id = NULL;
917 cpuid->core_id = NULL;
918 cpuid->hwthread_id = NULL;
919 cpuid->locality_order = NULL;
921 cpuid->vendor = cpuid_check_vendor();
923 switch (cpuid->vendor)
926 case GMX_CPUID_VENDOR_INTEL:
927 cpuid_check_intel_x86(cpuid);
929 case GMX_CPUID_VENDOR_AMD:
930 cpuid_check_amd_x86(cpuid);
935 strncpy(cpuid->brand, "Unknown CPU brand", GMX_CPUID_BRAND_MAXLEN);
936 #if defined(__linux__) || defined(__linux)
937 /* General Linux. Try to get CPU type from /proc/cpuinfo */
938 if ( (fp = fopen("/proc/cpuinfo", "r")) != NULL)
941 while ( (found_brand == 0) && (fgets(buffer, sizeof(buffer), fp) != NULL))
943 chomp_substring_before_colon(buffer, buffer2, sizeof(buffer2));
944 /* Intel uses "model name", Fujitsu and IBM "cpu". */
945 if (!strcmp(buffer2, "model name") || !strcmp(buffer2, "cpu"))
947 chomp_substring_after_colon(buffer, cpuid->brand, GMX_CPUID_BRAND_MAXLEN);
958 for (i = 0; i < GMX_CPUID_NFEATURES; i++)
960 cpuid->feature[i] = 0;
962 cpuid->feature[GMX_CPUID_FEATURE_CANNOTDETECT] = 1;
971 gmx_cpuid_done (gmx_cpuid_t cpuid)
978 gmx_cpuid_formatstring (gmx_cpuid_t cpuid,
984 enum gmx_cpuid_feature feature;
990 "Family: %2d Model: %2d Stepping: %2d\n"
992 gmx_cpuid_vendor_string[gmx_cpuid_vendor(cpuid)],
993 gmx_cpuid_brand(cpuid),
994 gmx_cpuid_family(cpuid), gmx_cpuid_model(cpuid), gmx_cpuid_stepping(cpuid));
999 "Family: %2d Model: %2d Stepping: %2d\n"
1001 gmx_cpuid_vendor_string[gmx_cpuid_vendor(cpuid)],
1002 gmx_cpuid_brand(cpuid),
1003 gmx_cpuid_family(cpuid), gmx_cpuid_model(cpuid), gmx_cpuid_stepping(cpuid));
1011 for (feature = GMX_CPUID_FEATURE_CANNOTDETECT; feature < GMX_CPUID_NFEATURES; feature++)
1013 if (gmx_cpuid_feature(cpuid, feature) == 1)
1016 _snprintf(str, n, " %s", gmx_cpuid_feature_string[feature]);
1018 snprintf(str, n, " %s", gmx_cpuid_feature_string[feature]);
1027 _snprintf(str, n, "\n");
1029 snprintf(str, n, "\n");
1039 gmx_cpuid_simd_suggest (gmx_cpuid_t cpuid)
1041 enum gmx_cpuid_simd tmpsimd;
1043 tmpsimd = GMX_CPUID_SIMD_NONE;
1045 if (gmx_cpuid_vendor(cpuid) == GMX_CPUID_VENDOR_INTEL)
1047 if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_AVX2))
1049 tmpsimd = GMX_CPUID_SIMD_X86_AVX2_256;
1051 else if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_AVX))
1053 tmpsimd = GMX_CPUID_SIMD_X86_AVX_256;
1055 else if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_SSE4_1))
1057 tmpsimd = GMX_CPUID_SIMD_X86_SSE4_1;
1059 else if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_SSE2))
1061 tmpsimd = GMX_CPUID_SIMD_X86_SSE2;
1064 else if (gmx_cpuid_vendor(cpuid) == GMX_CPUID_VENDOR_AMD)
1066 if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_AVX))
1068 tmpsimd = GMX_CPUID_SIMD_X86_AVX_128_FMA;
1070 else if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_SSE4_1))
1072 tmpsimd = GMX_CPUID_SIMD_X86_SSE4_1;
1074 else if (gmx_cpuid_feature(cpuid, GMX_CPUID_FEATURE_X86_SSE2))
1076 tmpsimd = GMX_CPUID_SIMD_X86_SSE2;
1079 else if (gmx_cpuid_vendor(cpuid) == GMX_CPUID_VENDOR_FUJITSU)
1081 if (strstr(gmx_cpuid_brand(cpuid), "SPARC64"))
1083 tmpsimd = GMX_CPUID_SIMD_SPARC64_HPC_ACE;
1086 else if (gmx_cpuid_vendor(cpuid) == GMX_CPUID_VENDOR_IBM)
1088 if (strstr(gmx_cpuid_brand(cpuid), "A2"))
1090 tmpsimd = GMX_CPUID_SIMD_IBM_QPX;
1099 gmx_cpuid_simd_check(gmx_cpuid_t cpuid,
1101 int print_to_stderr)
1105 enum gmx_cpuid_simd simd;
1107 simd = gmx_cpuid_simd_suggest(cpuid);
1109 rc = (simd != compiled_simd);
1111 gmx_cpuid_formatstring(cpuid, str, 1023);
1117 "\nDetecting CPU SIMD instructions.\nPresent hardware specification:\n"
1119 "SIMD instructions most likely to fit this hardware: %s\n"
1120 "SIMD instructions selected at GROMACS compile time: %s\n\n",
1122 gmx_cpuid_simd_string[simd],
1123 gmx_cpuid_simd_string[compiled_simd]);
1130 fprintf(log, "\nBinary not matching hardware - you might be losing performance.\n"
1131 "SIMD instructions most likely to fit this hardware: %s\n"
1132 "SIMD instructions selected at GROMACS compile time: %s\n\n",
1133 gmx_cpuid_simd_string[simd],
1134 gmx_cpuid_simd_string[compiled_simd]);
1136 if (print_to_stderr)
1138 fprintf(stderr, "Compiled SIMD instructions: %s (Gromacs could use %s on this machine, which is better)\n",
1139 gmx_cpuid_simd_string[compiled_simd],
1140 gmx_cpuid_simd_string[simd]);
1147 #ifdef GMX_CPUID_STANDALONE
1148 /* Stand-alone program to enable queries of CPU features from Cmake.
1149 * Note that you need to check inline ASM capabilities before compiling and set
1150 * -DGMX_X86_GCC_INLINE_ASM for the cpuid instruction to work...
1153 main(int argc, char **argv)
1156 enum gmx_cpuid_simd simd;
1162 "Usage:\n\n%s [flags]\n\n"
1163 "Available flags:\n"
1164 "-vendor Print CPU vendor.\n"
1165 "-brand Print CPU brand string.\n"
1166 "-family Print CPU family version.\n"
1167 "-model Print CPU model version.\n"
1168 "-stepping Print CPU stepping version.\n"
1169 "-features Print CPU feature flags.\n"
1170 "-simd Print suggested GROMACS SIMD instructions.\n",
1175 gmx_cpuid_init(&cpuid);
1177 if (!strncmp(argv[1], "-vendor", 3))
1179 printf("%s\n", gmx_cpuid_vendor_string[cpuid->vendor]);
1181 else if (!strncmp(argv[1], "-brand", 3))
1183 printf("%s\n", cpuid->brand);
1185 else if (!strncmp(argv[1], "-family", 3))
1187 printf("%d\n", cpuid->family);
1189 else if (!strncmp(argv[1], "-model", 3))
1191 printf("%d\n", cpuid->model);
1193 else if (!strncmp(argv[1], "-stepping", 3))
1195 printf("%d\n", cpuid->stepping);
1197 else if (!strncmp(argv[1], "-features", 3))
1200 for (i = 0; i < GMX_CPUID_NFEATURES; i++)
1202 if (cpuid->feature[i] == 1)
1208 printf("%s", gmx_cpuid_feature_string[i]);
1213 else if (!strncmp(argv[1], "-simd", 3))
1215 simd = gmx_cpuid_simd_suggest(cpuid);
1216 fprintf(stdout, "%s\n", gmx_cpuid_simd_string[simd]);
1219 gmx_cpuid_done(cpuid);