src/gromacs/ewald/pme_gpu_internal.cpp

   1 /*
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   3  *
   4  * Copyright (c) 2016,2017,2018,2019, by the GROMACS development team, led by
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  35
  36 /*! \internal \file
  37  *
  38  * \brief This file contains internal function implementations
  39  * for performing the PME calculations on GPU.
  40  *
  41  * Note that this file is compiled as regular C++ source in OpenCL builds, but
  42  * it is treated as CUDA source in CUDA-enabled GPU builds.
  43  *
  44  * \author Aleksei Iupinov <a.yupinov@gmail.com>
  45  * \ingroup module_ewald
  46  */
  47
  48 #include "gmxpre.h"
  49
  50 #include "pme_gpu_internal.h"
  51
  52 #include "config.h"
  53
  54 #include <list>
  55 #include <memory>
  56 #include <string>
  57
  58 #include "gromacs/ewald/ewald_utils.h"
  59 #include "gromacs/gpu_utils/gpu_utils.h"
  60 #include "gromacs/math/invertmatrix.h"
  61 #include "gromacs/math/units.h"
  62 #include "gromacs/timing/gpu_timing.h"
  63 #include "gromacs/utility/exceptions.h"
  64 #include "gromacs/utility/fatalerror.h"
  65 #include "gromacs/utility/gmxassert.h"
  66 #include "gromacs/utility/logger.h"
  67 #include "gromacs/utility/stringutil.h"
  68
  69 #if GMX_GPU == GMX_GPU_CUDA
  70 #include "gromacs/gpu_utils/pmalloc_cuda.h"
  71
  72 #include "pme.cuh"
  73 #elif GMX_GPU == GMX_GPU_OPENCL
  74 #include "gromacs/gpu_utils/gmxopencl.h"
  75 #endif
  76
  77 #include "gromacs/ewald/pme.h"
  78
  79 #include "pme_gpu_3dfft.h"
  80 #include "pme_gpu_constants.h"
  81 #include "pme_gpu_program_impl.h"
  82 #include "pme_gpu_timings.h"
  83 #include "pme_gpu_types.h"
  84 #include "pme_gpu_types_host.h"
  85 #include "pme_gpu_types_host_impl.h"
  86 #include "pme_gpu_utils.h"
  87 #include "pme_grid.h"
  88 #include "pme_internal.h"
  89 #include "pme_solve.h"
  90
  91 /*! \internal \brief
  92  * Wrapper for getting a pointer to the plain C++ part of the GPU kernel parameters structure.
  93  *
  94  * \param[in] pmeGpu  The PME GPU structure.
  95  * \returns The pointer to the kernel parameters.
  96  */
  97 static PmeGpuKernelParamsBase *pme_gpu_get_kernel_params_base_ptr(const PmeGpu *pmeGpu)
  98 {
  99     // reinterpret_cast is needed because the derived CUDA structure is not known in this file
 100     auto *kernelParamsPtr = reinterpret_cast<PmeGpuKernelParamsBase *>(pmeGpu->kernelParams.get());
 101     return kernelParamsPtr;
 102 }
 103
 104 int pme_gpu_get_atom_data_alignment(const PmeGpu * /*unused*/)
 105 {
 106     //TODO: this can be simplified, as c_pmeAtomDataAlignment is now constant
 107     if (c_usePadding)
 108     {
 109         return c_pmeAtomDataAlignment;
 110     }
 111     else
 112     {
 113         return 0;
 114     }
 115
 116 }
 117
 118 int pme_gpu_get_atoms_per_warp(const PmeGpu *pmeGpu)
 119 {
 120     return pmeGpu->programHandle_->impl_->warpSize / c_pmeSpreadGatherThreadsPerAtom;
 121 }
 122
 123 void pme_gpu_synchronize(const PmeGpu *pmeGpu)
 124 {
 125     gpuStreamSynchronize(pmeGpu->archSpecific->pmeStream);
 126 }
 127
 128 void pme_gpu_alloc_energy_virial(PmeGpu *pmeGpu)
 129 {
 130     const size_t energyAndVirialSize = c_virialAndEnergyCount * sizeof(float);
 131     allocateDeviceBuffer(&pmeGpu->kernelParams->constants.d_virialAndEnergy, c_virialAndEnergyCount, pmeGpu->archSpecific->context);
 132     pmalloc(reinterpret_cast<void **>(&pmeGpu->staging.h_virialAndEnergy), energyAndVirialSize);
 133 }
 134
 135 void pme_gpu_free_energy_virial(PmeGpu *pmeGpu)
 136 {
 137     freeDeviceBuffer(&pmeGpu->kernelParams->constants.d_virialAndEnergy);
 138     pfree(pmeGpu->staging.h_virialAndEnergy);
 139     pmeGpu->staging.h_virialAndEnergy = nullptr;
 140 }
 141
 142 void pme_gpu_clear_energy_virial(const PmeGpu *pmeGpu)
 143 {
 144     clearDeviceBufferAsync(&pmeGpu->kernelParams->constants.d_virialAndEnergy, 0,
 145                            c_virialAndEnergyCount, pmeGpu->archSpecific->pmeStream);
 146 }
 147
 148 void pme_gpu_realloc_and_copy_bspline_values(PmeGpu *pmeGpu)
 149 {
 150     const int splineValuesOffset[DIM] = {
 151         0,
 152         pmeGpu->kernelParams->grid.realGridSize[XX],
 153         pmeGpu->kernelParams->grid.realGridSize[XX] + pmeGpu->kernelParams->grid.realGridSize[YY]
 154     };
 155     memcpy(&pmeGpu->kernelParams->grid.splineValuesOffset, &splineValuesOffset, sizeof(splineValuesOffset));
 156
 157     const int newSplineValuesSize = pmeGpu->kernelParams->grid.realGridSize[XX] +
 158         pmeGpu->kernelParams->grid.realGridSize[YY] +
 159         pmeGpu->kernelParams->grid.realGridSize[ZZ];
 160     const bool shouldRealloc = (newSplineValuesSize > pmeGpu->archSpecific->splineValuesSize);
 161     reallocateDeviceBuffer(&pmeGpu->kernelParams->grid.d_splineModuli, newSplineValuesSize,
 162                            &pmeGpu->archSpecific->splineValuesSize, &pmeGpu->archSpecific->splineValuesSizeAlloc, pmeGpu->archSpecific->context);
 163     if (shouldRealloc)
 164     {
 165         /* Reallocate the host buffer */
 166         pfree(pmeGpu->staging.h_splineModuli);
 167         pmalloc(reinterpret_cast<void **>(&pmeGpu->staging.h_splineModuli), newSplineValuesSize * sizeof(float));
 168     }
 169     for (int i = 0; i < DIM; i++)
 170     {
 171         memcpy(pmeGpu->staging.h_splineModuli + splineValuesOffset[i], pmeGpu->common->bsp_mod[i].data(), pmeGpu->common->bsp_mod[i].size() * sizeof(float));
 172     }
 173     /* TODO: pin original buffer instead! */
 174     copyToDeviceBuffer(&pmeGpu->kernelParams->grid.d_splineModuli, pmeGpu->staging.h_splineModuli,
 175                        0, newSplineValuesSize,
 176                        pmeGpu->archSpecific->pmeStream, pmeGpu->settings.transferKind, nullptr);
 177 }
 178
 179 void pme_gpu_free_bspline_values(const PmeGpu *pmeGpu)
 180 {
 181     pfree(pmeGpu->staging.h_splineModuli);
 182     freeDeviceBuffer(&pmeGpu->kernelParams->grid.d_splineModuli);
 183 }
 184
 185 void pme_gpu_realloc_forces(PmeGpu *pmeGpu)
 186 {
 187     const size_t newForcesSize = pmeGpu->nAtomsAlloc * DIM;
 188     GMX_ASSERT(newForcesSize > 0, "Bad number of atoms in PME GPU");
 189     reallocateDeviceBuffer(&pmeGpu->kernelParams->atoms.d_forces, newForcesSize,
 190                            &pmeGpu->archSpecific->forcesSize, &pmeGpu->archSpecific->forcesSizeAlloc, pmeGpu->archSpecific->context);
 191     pmeGpu->staging.h_forces.reserveWithPadding(pmeGpu->nAtomsAlloc);
 192     pmeGpu->staging.h_forces.resizeWithPadding(pmeGpu->kernelParams->atoms.nAtoms);
 193 }
 194
 195 void pme_gpu_free_forces(const PmeGpu *pmeGpu)
 196 {
 197     freeDeviceBuffer(&pmeGpu->kernelParams->atoms.d_forces);
 198 }
 199
 200 void pme_gpu_copy_input_forces(PmeGpu *pmeGpu)
 201 {
 202     GMX_ASSERT(pmeGpu->kernelParams->atoms.nAtoms > 0, "Bad number of atoms in PME GPU");
 203     float *h_forcesFloat = reinterpret_cast<float *>(pmeGpu->staging.h_forces.data());
 204     copyToDeviceBuffer(&pmeGpu->kernelParams->atoms.d_forces, h_forcesFloat,
 205                        0, DIM * pmeGpu->kernelParams->atoms.nAtoms,
 206                        pmeGpu->archSpecific->pmeStream, pmeGpu->settings.transferKind, nullptr);
 207 }
 208
 209 void pme_gpu_copy_output_forces(PmeGpu *pmeGpu)
 210 {
 211     GMX_ASSERT(pmeGpu->kernelParams->atoms.nAtoms > 0, "Bad number of atoms in PME GPU");
 212     float *h_forcesFloat = reinterpret_cast<float *>(pmeGpu->staging.h_forces.data());
 213     copyFromDeviceBuffer(h_forcesFloat, &pmeGpu->kernelParams->atoms.d_forces,
 214                          0, DIM * pmeGpu->kernelParams->atoms.nAtoms,
 215                          pmeGpu->archSpecific->pmeStream, pmeGpu->settings.transferKind, nullptr);
 216 }
 217
 218 void pme_gpu_realloc_coordinates(const PmeGpu *pmeGpu)
 219 {
 220     const size_t newCoordinatesSize = pmeGpu->nAtomsAlloc * DIM;
 221     GMX_ASSERT(newCoordinatesSize > 0, "Bad number of atoms in PME GPU");
 222     reallocateDeviceBuffer(&pmeGpu->kernelParams->atoms.d_coordinates, newCoordinatesSize,
 223                            &pmeGpu->archSpecific->coordinatesSize, &pmeGpu->archSpecific->coordinatesSizeAlloc, pmeGpu->archSpecific->context);
 224     if (c_usePadding)
 225     {
 226         const size_t paddingIndex = DIM * pmeGpu->kernelParams->atoms.nAtoms;
 227         const size_t paddingCount = DIM * pmeGpu->nAtomsAlloc - paddingIndex;
 228         if (paddingCount > 0)
 229         {
 230             clearDeviceBufferAsync(&pmeGpu->kernelParams->atoms.d_coordinates, paddingIndex,
 231                                    paddingCount, pmeGpu->archSpecific->pmeStream);
 232         }
 233     }
 234 }
 235
 236 void pme_gpu_copy_input_coordinates(const PmeGpu *pmeGpu, const rvec *h_coordinates)
 237 {
 238     GMX_ASSERT(h_coordinates, "Bad host-side coordinate buffer in PME GPU");
 239 #if GMX_DOUBLE
 240     GMX_RELEASE_ASSERT(false, "Only single precision is supported");
 241     GMX_UNUSED_VALUE(h_coordinates);
 242 #else
 243     const float *h_coordinatesFloat = reinterpret_cast<const float *>(h_coordinates);
 244     copyToDeviceBuffer(&pmeGpu->kernelParams->atoms.d_coordinates, h_coordinatesFloat,
 245                        0, pmeGpu->kernelParams->atoms.nAtoms * DIM,
 246                        pmeGpu->archSpecific->pmeStream, pmeGpu->settings.transferKind, nullptr);
 247     // FIXME: sync required since the copied data will be used by PP stream when using single GPU for both
 248     //        Remove after adding the required event-based sync between the above H2D and the transform kernel
 249     pme_gpu_synchronize(pmeGpu);
 250 #endif
 251 }
 252
 253 void pme_gpu_free_coordinates(const PmeGpu *pmeGpu)
 254 {
 255     freeDeviceBuffer(&pmeGpu->kernelParams->atoms.d_coordinates);
 256 }
 257
 258 void pme_gpu_realloc_and_copy_input_coefficients(const PmeGpu *pmeGpu, const float *h_coefficients)
 259 {
 260     GMX_ASSERT(h_coefficients, "Bad host-side charge buffer in PME GPU");
 261     const size_t newCoefficientsSize = pmeGpu->nAtomsAlloc;
 262     GMX_ASSERT(newCoefficientsSize > 0, "Bad number of atoms in PME GPU");
 263     reallocateDeviceBuffer(&pmeGpu->kernelParams->atoms.d_coefficients, newCoefficientsSize,
 264                            &pmeGpu->archSpecific->coefficientsSize, &pmeGpu->archSpecific->coefficientsSizeAlloc, pmeGpu->archSpecific->context);
 265     copyToDeviceBuffer(&pmeGpu->kernelParams->atoms.d_coefficients, const_cast<float *>(h_coefficients),
 266                        0, pmeGpu->kernelParams->atoms.nAtoms,
 267                        pmeGpu->archSpecific->pmeStream, pmeGpu->settings.transferKind, nullptr);
 268     if (c_usePadding)
 269     {
 270         const size_t paddingIndex = pmeGpu->kernelParams->atoms.nAtoms;
 271         const size_t paddingCount = pmeGpu->nAtomsAlloc - paddingIndex;
 272         if (paddingCount > 0)
 273         {
 274             clearDeviceBufferAsync(&pmeGpu->kernelParams->atoms.d_coefficients, paddingIndex,
 275                                    paddingCount, pmeGpu->archSpecific->pmeStream);
 276         }
 277     }
 278 }
 279
 280 void pme_gpu_free_coefficients(const PmeGpu *pmeGpu)
 281 {
 282     freeDeviceBuffer(&pmeGpu->kernelParams->atoms.d_coefficients);
 283 }
 284
 285 void pme_gpu_realloc_spline_data(PmeGpu *pmeGpu)
 286 {
 287     const int    order             = pmeGpu->common->pme_order;
 288     const int    alignment         = pme_gpu_get_atoms_per_warp(pmeGpu);
 289     const size_t nAtomsPadded      = ((pmeGpu->nAtomsAlloc + alignment - 1) / alignment) * alignment;
 290     const int    newSplineDataSize = DIM * order * nAtomsPadded;
 291     GMX_ASSERT(newSplineDataSize > 0, "Bad number of atoms in PME GPU");
 292     /* Two arrays of the same size */
 293     const bool shouldRealloc        = (newSplineDataSize > pmeGpu->archSpecific->splineDataSize);
 294     int        currentSizeTemp      = pmeGpu->archSpecific->splineDataSize;
 295     int        currentSizeTempAlloc = pmeGpu->archSpecific->splineDataSizeAlloc;
 296     reallocateDeviceBuffer(&pmeGpu->kernelParams->atoms.d_theta, newSplineDataSize,
 297                            &currentSizeTemp, &currentSizeTempAlloc, pmeGpu->archSpecific->context);
 298     reallocateDeviceBuffer(&pmeGpu->kernelParams->atoms.d_dtheta, newSplineDataSize,
 299                            &pmeGpu->archSpecific->splineDataSize, &pmeGpu->archSpecific->splineDataSizeAlloc, pmeGpu->archSpecific->context);
 300     // the host side reallocation
 301     if (shouldRealloc)
 302     {
 303         pfree(pmeGpu->staging.h_theta);
 304         pmalloc(reinterpret_cast<void **>(&pmeGpu->staging.h_theta), newSplineDataSize * sizeof(float));
 305         pfree(pmeGpu->staging.h_dtheta);
 306         pmalloc(reinterpret_cast<void **>(&pmeGpu->staging.h_dtheta), newSplineDataSize * sizeof(float));
 307     }
 308 }
 309
 310 void pme_gpu_free_spline_data(const PmeGpu *pmeGpu)
 311 {
 312     /* Two arrays of the same size */
 313     freeDeviceBuffer(&pmeGpu->kernelParams->atoms.d_theta);
 314     freeDeviceBuffer(&pmeGpu->kernelParams->atoms.d_dtheta);
 315     pfree(pmeGpu->staging.h_theta);
 316     pfree(pmeGpu->staging.h_dtheta);
 317 }
 318
 319 void pme_gpu_realloc_grid_indices(PmeGpu *pmeGpu)
 320 {
 321     const size_t newIndicesSize = DIM * pmeGpu->nAtomsAlloc;
 322     GMX_ASSERT(newIndicesSize > 0, "Bad number of atoms in PME GPU");
 323     reallocateDeviceBuffer(&pmeGpu->kernelParams->atoms.d_gridlineIndices, newIndicesSize,
 324                            &pmeGpu->archSpecific->gridlineIndicesSize, &pmeGpu->archSpecific->gridlineIndicesSizeAlloc, pmeGpu->archSpecific->context);
 325     pfree(pmeGpu->staging.h_gridlineIndices);
 326     pmalloc(reinterpret_cast<void **>(&pmeGpu->staging.h_gridlineIndices), newIndicesSize * sizeof(int));
 327 }
 328
 329 void pme_gpu_free_grid_indices(const PmeGpu *pmeGpu)
 330 {
 331     freeDeviceBuffer(&pmeGpu->kernelParams->atoms.d_gridlineIndices);
 332     pfree(pmeGpu->staging.h_gridlineIndices);
 333 }
 334
 335 void pme_gpu_realloc_grids(PmeGpu *pmeGpu)
 336 {
 337     auto     *kernelParamsPtr = pmeGpu->kernelParams.get();
 338     const int newRealGridSize = kernelParamsPtr->grid.realGridSizePadded[XX] *
 339         kernelParamsPtr->grid.realGridSizePadded[YY] *
 340         kernelParamsPtr->grid.realGridSizePadded[ZZ];
 341     const int newComplexGridSize = kernelParamsPtr->grid.complexGridSizePadded[XX] *
 342         kernelParamsPtr->grid.complexGridSizePadded[YY] *
 343         kernelParamsPtr->grid.complexGridSizePadded[ZZ] * 2;
 344     // Multiplied by 2 because we count complex grid size for complex numbers, but all allocations/pointers are float
 345     if (pmeGpu->archSpecific->performOutOfPlaceFFT)
 346     {
 347         /* 2 separate grids */
 348         reallocateDeviceBuffer(&kernelParamsPtr->grid.d_fourierGrid, newComplexGridSize,
 349                                &pmeGpu->archSpecific->complexGridSize, &pmeGpu->archSpecific->complexGridSizeAlloc, pmeGpu->archSpecific->context);
 350         reallocateDeviceBuffer(&kernelParamsPtr->grid.d_realGrid, newRealGridSize,
 351                                &pmeGpu->archSpecific->realGridSize, &pmeGpu->archSpecific->realGridSizeAlloc, pmeGpu->archSpecific->context);
 352     }
 353     else
 354     {
 355         /* A single buffer so that any grid will fit */
 356         const int newGridsSize = std::max(newRealGridSize, newComplexGridSize);
 357         reallocateDeviceBuffer(&kernelParamsPtr->grid.d_realGrid, newGridsSize,
 358                                &pmeGpu->archSpecific->realGridSize, &pmeGpu->archSpecific->realGridSizeAlloc, pmeGpu->archSpecific->context);
 359         kernelParamsPtr->grid.d_fourierGrid   = kernelParamsPtr->grid.d_realGrid;
 360         pmeGpu->archSpecific->complexGridSize = pmeGpu->archSpecific->realGridSize;
 361         // the size might get used later for copying the grid
 362     }
 363 }
 364
 365 void pme_gpu_free_grids(const PmeGpu *pmeGpu)
 366 {
 367     if (pmeGpu->archSpecific->performOutOfPlaceFFT)
 368     {
 369         freeDeviceBuffer(&pmeGpu->kernelParams->grid.d_fourierGrid);
 370     }
 371     freeDeviceBuffer(&pmeGpu->kernelParams->grid.d_realGrid);
 372 }
 373
 374 void pme_gpu_clear_grids(const PmeGpu *pmeGpu)
 375 {
 376     clearDeviceBufferAsync(&pmeGpu->kernelParams->grid.d_realGrid, 0,
 377                            pmeGpu->archSpecific->realGridSize, pmeGpu->archSpecific->pmeStream);
 378 }
 379
 380 void pme_gpu_realloc_and_copy_fract_shifts(PmeGpu *pmeGpu)
 381 {
 382     pme_gpu_free_fract_shifts(pmeGpu);
 383
 384     auto        *kernelParamsPtr = pmeGpu->kernelParams.get();
 385
 386     const int    nx                  = kernelParamsPtr->grid.realGridSize[XX];
 387     const int    ny                  = kernelParamsPtr->grid.realGridSize[YY];
 388     const int    nz                  = kernelParamsPtr->grid.realGridSize[ZZ];
 389     const int    cellCount           = c_pmeNeighborUnitcellCount;
 390     const int    gridDataOffset[DIM] = {0, cellCount * nx, cellCount * (nx + ny)};
 391
 392     memcpy(kernelParamsPtr->grid.tablesOffsets, &gridDataOffset, sizeof(gridDataOffset));
 393
 394     const int    newFractShiftsSize  = cellCount * (nx + ny + nz);
 395
 396 #if GMX_GPU == GMX_GPU_CUDA
 397     initParamLookupTable(kernelParamsPtr->grid.d_fractShiftsTable,
 398                          kernelParamsPtr->fractShiftsTableTexture,
 399                          pmeGpu->common->fsh.data(),
 400                          newFractShiftsSize);
 401
 402     initParamLookupTable(kernelParamsPtr->grid.d_gridlineIndicesTable,
 403                          kernelParamsPtr->gridlineIndicesTableTexture,
 404                          pmeGpu->common->nn.data(),
 405                          newFractShiftsSize);
 406 #elif GMX_GPU == GMX_GPU_OPENCL
 407     // No dedicated texture routines....
 408     allocateDeviceBuffer(&kernelParamsPtr->grid.d_fractShiftsTable, newFractShiftsSize, pmeGpu->archSpecific->context);
 409     allocateDeviceBuffer(&kernelParamsPtr->grid.d_gridlineIndicesTable, newFractShiftsSize, pmeGpu->archSpecific->context);
 410     copyToDeviceBuffer(&kernelParamsPtr->grid.d_fractShiftsTable, pmeGpu->common->fsh.data(),
 411                        0, newFractShiftsSize,
 412                        pmeGpu->archSpecific->pmeStream, GpuApiCallBehavior::Async, nullptr);
 413     copyToDeviceBuffer(&kernelParamsPtr->grid.d_gridlineIndicesTable, pmeGpu->common->nn.data(),
 414                        0, newFractShiftsSize,
 415                        pmeGpu->archSpecific->pmeStream, GpuApiCallBehavior::Async, nullptr);
 416 #endif
 417 }
 418
 419 void pme_gpu_free_fract_shifts(const PmeGpu *pmeGpu)
 420 {
 421     auto *kernelParamsPtr = pmeGpu->kernelParams.get();
 422 #if GMX_GPU == GMX_GPU_CUDA
 423     destroyParamLookupTable(kernelParamsPtr->grid.d_fractShiftsTable,
 424                             kernelParamsPtr->fractShiftsTableTexture);
 425     destroyParamLookupTable(kernelParamsPtr->grid.d_gridlineIndicesTable,
 426                             kernelParamsPtr->gridlineIndicesTableTexture);
 427 #elif GMX_GPU == GMX_GPU_OPENCL
 428     freeDeviceBuffer(&kernelParamsPtr->grid.d_fractShiftsTable);
 429     freeDeviceBuffer(&kernelParamsPtr->grid.d_gridlineIndicesTable);
 430 #endif
 431 }
 432
 433 bool pme_gpu_stream_query(const PmeGpu *pmeGpu)
 434 {
 435     return haveStreamTasksCompleted(pmeGpu->archSpecific->pmeStream);
 436 }
 437
 438 void pme_gpu_copy_input_gather_grid(const PmeGpu *pmeGpu, float *h_grid)
 439 {
 440     copyToDeviceBuffer(&pmeGpu->kernelParams->grid.d_realGrid, h_grid,
 441                        0, pmeGpu->archSpecific->realGridSize,
 442                        pmeGpu->archSpecific->pmeStream, pmeGpu->settings.transferKind, nullptr);
 443 }
 444
 445 void pme_gpu_copy_output_spread_grid(const PmeGpu *pmeGpu, float *h_grid)
 446 {
 447     copyFromDeviceBuffer(h_grid, &pmeGpu->kernelParams->grid.d_realGrid,
 448                          0, pmeGpu->archSpecific->realGridSize,
 449                          pmeGpu->archSpecific->pmeStream, pmeGpu->settings.transferKind, nullptr);
 450     pmeGpu->archSpecific->syncSpreadGridD2H.markEvent(pmeGpu->archSpecific->pmeStream);
 451 }
 452
 453 void pme_gpu_copy_output_spread_atom_data(const PmeGpu *pmeGpu)
 454 {
 455     const int    alignment        = pme_gpu_get_atoms_per_warp(pmeGpu);
 456     const size_t nAtomsPadded     = ((pmeGpu->nAtomsAlloc + alignment - 1) / alignment) * alignment;
 457     const size_t splinesCount     = DIM * nAtomsPadded * pmeGpu->common->pme_order;
 458     auto        *kernelParamsPtr  = pmeGpu->kernelParams.get();
 459     copyFromDeviceBuffer(pmeGpu->staging.h_dtheta, &kernelParamsPtr->atoms.d_dtheta,
 460                          0, splinesCount,
 461                          pmeGpu->archSpecific->pmeStream, pmeGpu->settings.transferKind, nullptr);
 462     copyFromDeviceBuffer(pmeGpu->staging.h_theta, &kernelParamsPtr->atoms.d_theta,
 463                          0, splinesCount,
 464                          pmeGpu->archSpecific->pmeStream, pmeGpu->settings.transferKind, nullptr);
 465     copyFromDeviceBuffer(pmeGpu->staging.h_gridlineIndices, &kernelParamsPtr->atoms.d_gridlineIndices,
 466                          0, kernelParamsPtr->atoms.nAtoms * DIM,
 467                          pmeGpu->archSpecific->pmeStream, pmeGpu->settings.transferKind, nullptr);
 468 }
 469
 470 void pme_gpu_copy_input_gather_atom_data(const PmeGpu *pmeGpu)
 471 {
 472     const int    alignment       = pme_gpu_get_atoms_per_warp(pmeGpu);
 473     const size_t nAtomsPadded    = ((pmeGpu->nAtomsAlloc + alignment - 1) / alignment) * alignment;
 474     const size_t splinesCount    = DIM * nAtomsPadded * pmeGpu->common->pme_order;
 475     auto        *kernelParamsPtr = pmeGpu->kernelParams.get();
 476     if (c_usePadding)
 477     {
 478         // TODO: could clear only the padding and not the whole thing, but this is a test-exclusive code anyway
 479         clearDeviceBufferAsync(&kernelParamsPtr->atoms.d_gridlineIndices, 0,
 480                                pmeGpu->nAtomsAlloc * DIM, pmeGpu->archSpecific->pmeStream);
 481         clearDeviceBufferAsync(&kernelParamsPtr->atoms.d_dtheta, 0,
 482                                pmeGpu->nAtomsAlloc * pmeGpu->common->pme_order * DIM, pmeGpu->archSpecific->pmeStream);
 483         clearDeviceBufferAsync(&kernelParamsPtr->atoms.d_theta, 0,
 484                                pmeGpu->nAtomsAlloc * pmeGpu->common->pme_order * DIM, pmeGpu->archSpecific->pmeStream);
 485     }
 486     copyToDeviceBuffer(&kernelParamsPtr->atoms.d_dtheta, pmeGpu->staging.h_dtheta,
 487                        0, splinesCount,
 488                        pmeGpu->archSpecific->pmeStream, pmeGpu->settings.transferKind, nullptr);
 489     copyToDeviceBuffer(&kernelParamsPtr->atoms.d_theta, pmeGpu->staging.h_theta,
 490                        0, splinesCount,
 491                        pmeGpu->archSpecific->pmeStream, pmeGpu->settings.transferKind, nullptr);
 492     copyToDeviceBuffer(&kernelParamsPtr->atoms.d_gridlineIndices, pmeGpu->staging.h_gridlineIndices,
 493                        0, kernelParamsPtr->atoms.nAtoms * DIM,
 494                        pmeGpu->archSpecific->pmeStream, pmeGpu->settings.transferKind, nullptr);
 495 }
 496
 497 void pme_gpu_sync_spread_grid(const PmeGpu *pmeGpu)
 498 {
 499     pmeGpu->archSpecific->syncSpreadGridD2H.waitForEvent();
 500 }
 501
 502 void pme_gpu_init_internal(PmeGpu *pmeGpu)
 503 {
 504 #if GMX_GPU == GMX_GPU_CUDA
 505     // Prepare to use the device that this PME task was assigned earlier.
 506     // Other entities, such as CUDA timing events, are known to implicitly use the device context.
 507     CU_RET_ERR(cudaSetDevice(pmeGpu->deviceInfo->id), "Switching to PME CUDA device");
 508 #endif
 509
 510     /* Allocate the target-specific structures */
 511     pmeGpu->archSpecific.reset(new PmeGpuSpecific());
 512     pmeGpu->kernelParams.reset(new PmeGpuKernelParams());
 513
 514     pmeGpu->archSpecific->performOutOfPlaceFFT = true;
 515     /* This should give better performance, according to the cuFFT documentation.
 516      * The performance seems to be the same though.
 517      * TODO: PME could also try to pick up nice grid sizes (with factors of 2, 3, 5, 7).
 518      */
 519
 520     // TODO: this is just a convenient reuse because programHandle_ currently is in charge of creating context
 521     pmeGpu->archSpecific->context = pmeGpu->programHandle_->impl_->context;
 522
 523     // timing enabling - TODO put this in gpu_utils (even though generally this is just option handling?) and reuse in NB
 524     if (GMX_GPU == GMX_GPU_CUDA)
 525     {
 526         /* WARNING: CUDA timings are incorrect with multiple streams.
 527          *          This is the main reason why they are disabled by default.
 528          */
 529         // TODO: Consider turning on by default when we can detect nr of streams.
 530         pmeGpu->archSpecific->useTiming = (getenv("GMX_ENABLE_GPU_TIMING") != nullptr);
 531     }
 532     else if (GMX_GPU == GMX_GPU_OPENCL)
 533     {
 534         pmeGpu->archSpecific->useTiming = (getenv("GMX_DISABLE_GPU_TIMING") == nullptr);
 535     }
 536
 537 #if GMX_GPU == GMX_GPU_CUDA
 538     pmeGpu->maxGridWidthX = pmeGpu->deviceInfo->prop.maxGridSize[0];
 539 #elif GMX_GPU == GMX_GPU_OPENCL
 540     pmeGpu->maxGridWidthX = INT32_MAX / 2;
 541     // TODO: is there no really global work size limit in OpenCL?
 542 #endif
 543
 544     /* Creating a PME GPU stream:
 545      * - default high priority with CUDA
 546      * - no priorities implemented yet with OpenCL; see #2532
 547      */
 548 #if GMX_GPU == GMX_GPU_CUDA
 549     cudaError_t stat;
 550     int         highest_priority, lowest_priority;
 551     stat = cudaDeviceGetStreamPriorityRange(&lowest_priority, &highest_priority);
 552     CU_RET_ERR(stat, "PME cudaDeviceGetStreamPriorityRange failed");
 553     stat = cudaStreamCreateWithPriority(&pmeGpu->archSpecific->pmeStream,
 554                                         cudaStreamDefault, //cudaStreamNonBlocking,
 555                                         highest_priority);
 556     CU_RET_ERR(stat, "cudaStreamCreateWithPriority on the PME stream failed");
 557 #elif GMX_GPU == GMX_GPU_OPENCL
 558     cl_command_queue_properties queueProperties = pmeGpu->archSpecific->useTiming ? CL_QUEUE_PROFILING_ENABLE : 0;
 559     cl_device_id                device_id       = pmeGpu->deviceInfo->ocl_gpu_id.ocl_device_id;
 560     cl_int                      clError;
 561     pmeGpu->archSpecific->pmeStream = clCreateCommandQueue(pmeGpu->archSpecific->context,
 562                                                            device_id, queueProperties, &clError);
 563     if (clError != CL_SUCCESS)
 564     {
 565         GMX_THROW(gmx::InternalError("Failed to create PME command queue"));
 566     }
 567 #endif
 568 }
 569
 570 void pme_gpu_destroy_specific(const PmeGpu *pmeGpu)
 571 {
 572 #if GMX_GPU == GMX_GPU_CUDA
 573     /* Destroy the CUDA stream */
 574     cudaError_t stat = cudaStreamDestroy(pmeGpu->archSpecific->pmeStream);
 575     CU_RET_ERR(stat, "PME cudaStreamDestroy error");
 576 #elif GMX_GPU == GMX_GPU_OPENCL
 577     cl_int clError = clReleaseCommandQueue(pmeGpu->archSpecific->pmeStream);
 578     if (clError != CL_SUCCESS)
 579     {
 580         gmx_warning("Failed to destroy PME command queue");
 581     }
 582 #endif
 583 }
 584
 585 void pme_gpu_reinit_3dfft(const PmeGpu *pmeGpu)
 586 {
 587     if (pme_gpu_performs_FFT(pmeGpu))
 588     {
 589         pmeGpu->archSpecific->fftSetup.resize(0);
 590         for (int i = 0; i < pmeGpu->common->ngrids; i++)
 591         {
 592             pmeGpu->archSpecific->fftSetup.push_back(std::make_unique<GpuParallel3dFft>(pmeGpu));
 593         }
 594     }
 595 }
 596
 597 void pme_gpu_destroy_3dfft(const PmeGpu *pmeGpu)
 598 {
 599     pmeGpu->archSpecific->fftSetup.resize(0);
 600 }
 601
 602 int getSplineParamFullIndex(int order, int splineIndex, int dimIndex, int atomIndex, int atomsPerWarp)
 603 {
 604     if (order != c_pmeGpuOrder)
 605     {
 606         throw order;
 607     }
 608     constexpr int fixedOrder = c_pmeGpuOrder;
 609     GMX_UNUSED_VALUE(fixedOrder);
 610
 611     const int atomWarpIndex = atomIndex % atomsPerWarp;
 612     const int warpIndex     = atomIndex / atomsPerWarp;
 613     int       indexBase, result;
 614     switch (atomsPerWarp)
 615     {
 616         case 1:
 617             indexBase = getSplineParamIndexBase<fixedOrder, 1>(warpIndex, atomWarpIndex);
 618             result    = getSplineParamIndex<fixedOrder, 1>(indexBase, dimIndex, splineIndex);
 619             break;
 620
 621         case 2:
 622             indexBase = getSplineParamIndexBase<fixedOrder, 2>(warpIndex, atomWarpIndex);
 623             result    = getSplineParamIndex<fixedOrder, 2>(indexBase, dimIndex, splineIndex);
 624             break;
 625
 626         case 4:
 627             indexBase = getSplineParamIndexBase<fixedOrder, 4>(warpIndex, atomWarpIndex);
 628             result    = getSplineParamIndex<fixedOrder, 4>(indexBase, dimIndex, splineIndex);
 629             break;
 630
 631         case 8:
 632             indexBase = getSplineParamIndexBase<fixedOrder, 8>(warpIndex, atomWarpIndex);
 633             result    = getSplineParamIndex<fixedOrder, 8>(indexBase, dimIndex, splineIndex);
 634             break;
 635
 636         default:
 637             GMX_THROW(gmx::NotImplementedError(gmx::formatString("Test function call not unrolled for atomsPerWarp = %d in getSplineParamFullIndex", atomsPerWarp)));
 638     }
 639     return result;
 640 }
 641
 642 PmeOutput pme_gpu_getEnergyAndVirial(const gmx_pme_t &pme)
 643 {
 644     PmeOutput     output;
 645
 646     const PmeGpu *pmeGpu = pme.gpu;
 647     for (int j = 0; j < c_virialAndEnergyCount; j++)
 648     {
 649         GMX_ASSERT(std::isfinite(pmeGpu->staging.h_virialAndEnergy[j]), "PME GPU produces incorrect energy/virial.");
 650     }
 651
 652     unsigned int j = 0;
 653     output.coulombVirial_[XX][XX] = 0.25F * pmeGpu->staging.h_virialAndEnergy[j++];
 654     output.coulombVirial_[YY][YY] = 0.25F * pmeGpu->staging.h_virialAndEnergy[j++];
 655     output.coulombVirial_[ZZ][ZZ] = 0.25F * pmeGpu->staging.h_virialAndEnergy[j++];
 656     output.coulombVirial_[XX][YY] = output.coulombVirial_[YY][XX] = 0.25F * pmeGpu->staging.h_virialAndEnergy[j++];
 657     output.coulombVirial_[XX][ZZ] = output.coulombVirial_[ZZ][XX] = 0.25F * pmeGpu->staging.h_virialAndEnergy[j++];
 658     output.coulombVirial_[YY][ZZ] = output.coulombVirial_[ZZ][YY] = 0.25F * pmeGpu->staging.h_virialAndEnergy[j++];
 659     output.coulombEnergy_         = 0.5F * pmeGpu->staging.h_virialAndEnergy[j++];
 660
 661     return output;
 662 }
 663
 664 PmeOutput pme_gpu_getOutput(const gmx_pme_t &pme,
 665                             const int        flags)
 666 {
 667     PmeGpu    *pmeGpu = pme.gpu;
 668     const bool haveComputedEnergyAndVirial = (flags & GMX_PME_CALC_ENER_VIR) != 0;
 669     if (!haveComputedEnergyAndVirial)
 670     {
 671         // The caller knows from the flags that the energy and the virial are not usable
 672         PmeOutput output;
 673         output.forces_ = pmeGpu->staging.h_forces;
 674         return output;
 675     }
 676
 677     if (pme_gpu_performs_solve(pmeGpu))
 678     {
 679         PmeOutput output = pme_gpu_getEnergyAndVirial(pme);
 680         output.forces_ = pmeGpu->staging.h_forces;
 681         return output;
 682     }
 683     else
 684     {
 685         PmeOutput output;
 686         get_pme_ener_vir_q(pme.solve_work, pme.nthread, &output);
 687         output.forces_ = pmeGpu->staging.h_forces;
 688         return output;
 689     }
 690
 691 }
 692
 693 void pme_gpu_update_input_box(PmeGpu gmx_unused       *pmeGpu,
 694                               const matrix gmx_unused  box)
 695 {
 696 #if GMX_DOUBLE
 697     GMX_THROW(gmx::NotImplementedError("PME is implemented for single-precision only on GPU"));
 698 #else
 699     matrix  scaledBox;
 700     pmeGpu->common->boxScaler->scaleBox(box, scaledBox);
 701     auto   *kernelParamsPtr      = pme_gpu_get_kernel_params_base_ptr(pmeGpu);
 702     kernelParamsPtr->current.boxVolume = scaledBox[XX][XX] * scaledBox[YY][YY] * scaledBox[ZZ][ZZ];
 703     GMX_ASSERT(kernelParamsPtr->current.boxVolume != 0.0F, "Zero volume of the unit cell");
 704     matrix recipBox;
 705     gmx::invertBoxMatrix(scaledBox, recipBox);
 706
 707     /* The GPU recipBox is transposed as compared to the CPU recipBox.
 708      * Spread uses matrix columns (while solve and gather use rows).
 709      * There is no particular reason for this; it might be further rethought/optimized for better access patterns.
 710      */
 711     const real newRecipBox[DIM][DIM] =
 712     {
 713         {recipBox[XX][XX], recipBox[YY][XX], recipBox[ZZ][XX]},
 714         {             0.0, recipBox[YY][YY], recipBox[ZZ][YY]},
 715         {             0.0,              0.0, recipBox[ZZ][ZZ]}
 716     };
 717     memcpy(kernelParamsPtr->current.recipBox, newRecipBox, sizeof(matrix));
 718 #endif
 719 }
 720
 721 /*! \brief \libinternal
 722  * (Re-)initializes all the PME GPU data related to the grid size and cut-off.
 723  *
 724  * \param[in] pmeGpu            The PME GPU structure.
 725  */
 726 static void pme_gpu_reinit_grids(PmeGpu *pmeGpu)
 727 {
 728     auto *kernelParamsPtr = pme_gpu_get_kernel_params_base_ptr(pmeGpu);
 729     kernelParamsPtr->grid.ewaldFactor = (M_PI * M_PI) / (pmeGpu->common->ewaldcoeff_q * pmeGpu->common->ewaldcoeff_q);
 730
 731     /* The grid size variants */
 732     for (int i = 0; i < DIM; i++)
 733     {
 734         kernelParamsPtr->grid.realGridSize[i]       = pmeGpu->common->nk[i];
 735         kernelParamsPtr->grid.realGridSizeFP[i]     = static_cast<float>(kernelParamsPtr->grid.realGridSize[i]);
 736         kernelParamsPtr->grid.realGridSizePadded[i] = kernelParamsPtr->grid.realGridSize[i];
 737
 738         // The complex grid currently uses no padding;
 739         // if it starts to do so, then another test should be added for that
 740         kernelParamsPtr->grid.complexGridSize[i]       = kernelParamsPtr->grid.realGridSize[i];
 741         kernelParamsPtr->grid.complexGridSizePadded[i] = kernelParamsPtr->grid.realGridSize[i];
 742     }
 743     /* FFT: n real elements correspond to (n / 2 + 1) complex elements in minor dimension */
 744     if (!pme_gpu_performs_FFT(pmeGpu))
 745     {
 746         // This allows for GPU spreading grid and CPU fftgrid to have the same layout, so that we can copy the data directly
 747         kernelParamsPtr->grid.realGridSizePadded[ZZ] = (kernelParamsPtr->grid.realGridSize[ZZ] / 2 + 1) * 2;
 748     }
 749
 750     /* GPU FFT: n real elements correspond to (n / 2 + 1) complex elements in minor dimension */
 751     kernelParamsPtr->grid.complexGridSize[ZZ] /= 2;
 752     kernelParamsPtr->grid.complexGridSize[ZZ]++;
 753     kernelParamsPtr->grid.complexGridSizePadded[ZZ] = kernelParamsPtr->grid.complexGridSize[ZZ];
 754
 755     pme_gpu_realloc_and_copy_fract_shifts(pmeGpu);
 756     pme_gpu_realloc_and_copy_bspline_values(pmeGpu);
 757     pme_gpu_realloc_grids(pmeGpu);
 758     pme_gpu_reinit_3dfft(pmeGpu);
 759 }
 760
 761 /* Several GPU functions that refer to the CPU PME data live here.
 762  * We would like to keep these away from the GPU-framework specific code for clarity,
 763  * as well as compilation issues with MPI.
 764  */
 765
 766 /*! \brief \libinternal
 767  * Copies everything useful from the PME CPU to the PME GPU structure.
 768  * The goal is to minimize interaction with the PME CPU structure in the GPU code.
 769  *
 770  * \param[in] pme         The PME structure.
 771  */
 772 static void pme_gpu_copy_common_data_from(const gmx_pme_t *pme)
 773 {
 774     /* TODO: Consider refactoring the CPU PME code to use the same structure,
 775      * so that this function becomes 2 lines */
 776     PmeGpu *pmeGpu             = pme->gpu;
 777     pmeGpu->common->ngrids        = pme->ngrids;
 778     pmeGpu->common->epsilon_r     = pme->epsilon_r;
 779     pmeGpu->common->ewaldcoeff_q  = pme->ewaldcoeff_q;
 780     pmeGpu->common->nk[XX]        = pme->nkx;
 781     pmeGpu->common->nk[YY]        = pme->nky;
 782     pmeGpu->common->nk[ZZ]        = pme->nkz;
 783     pmeGpu->common->pme_order     = pme->pme_order;
 784     if (pmeGpu->common->pme_order != c_pmeGpuOrder)
 785     {
 786         GMX_THROW(gmx::NotImplementedError("pme_order != 4 is not implemented!"));
 787     }
 788     for (int i = 0; i < DIM; i++)
 789     {
 790         pmeGpu->common->bsp_mod[i].assign(pme->bsp_mod[i], pme->bsp_mod[i] + pmeGpu->common->nk[i]);
 791     }
 792     const int cellCount = c_pmeNeighborUnitcellCount;
 793     pmeGpu->common->fsh.resize(0);
 794     pmeGpu->common->fsh.insert(pmeGpu->common->fsh.end(), pme->fshx, pme->fshx + cellCount * pme->nkx);
 795     pmeGpu->common->fsh.insert(pmeGpu->common->fsh.end(), pme->fshy, pme->fshy + cellCount * pme->nky);
 796     pmeGpu->common->fsh.insert(pmeGpu->common->fsh.end(), pme->fshz, pme->fshz + cellCount * pme->nkz);
 797     pmeGpu->common->nn.resize(0);
 798     pmeGpu->common->nn.insert(pmeGpu->common->nn.end(), pme->nnx, pme->nnx + cellCount * pme->nkx);
 799     pmeGpu->common->nn.insert(pmeGpu->common->nn.end(), pme->nny, pme->nny + cellCount * pme->nky);
 800     pmeGpu->common->nn.insert(pmeGpu->common->nn.end(), pme->nnz, pme->nnz + cellCount * pme->nkz);
 801     pmeGpu->common->runMode   = pme->runMode;
 802     pmeGpu->common->boxScaler = pme->boxScaler;
 803 }
 804
 805 /*! \libinternal \brief
 806  * Initializes the PME GPU data at the beginning of the run.
 807  * TODO: this should become PmeGpu::PmeGpu()
 808  *
 809  * \param[in,out] pme            The PME structure.
 810  * \param[in,out] gpuInfo        The GPU information structure.
 811  * \param[in]     pmeGpuProgram  The handle to the program/kernel data created outside (e.g. in unit tests/runner)
 812  */
 813 static void pme_gpu_init(gmx_pme_t               *pme,
 814                          const gmx_device_info_t *gpuInfo,
 815                          PmeGpuProgramHandle      pmeGpuProgram)
 816 {
 817     pme->gpu          = new PmeGpu();
 818     PmeGpu *pmeGpu = pme->gpu;
 819     changePinningPolicy(&pmeGpu->staging.h_forces, pme_get_pinning_policy());
 820     pmeGpu->common = std::make_shared<PmeShared>();
 821
 822     /* These settings are set here for the whole run; dynamic ones are set in pme_gpu_reinit() */
 823     /* A convenience variable. */
 824     pmeGpu->settings.useDecomposition = (pme->nnodes == 1);
 825     /* TODO: CPU gather with GPU spread is broken due to different theta/dtheta layout. */
 826     pmeGpu->settings.performGPUGather = true;
 827
 828     pme_gpu_set_testing(pmeGpu, false);
 829
 830     pmeGpu->deviceInfo = gpuInfo;
 831     GMX_ASSERT(pmeGpuProgram != nullptr, "GPU kernels must be already compiled");
 832     pmeGpu->programHandle_ = pmeGpuProgram;
 833
 834     pmeGpu->initializedClfftLibrary_ = std::make_unique<gmx::ClfftInitializer>();
 835
 836     pme_gpu_init_internal(pmeGpu);
 837     pme_gpu_alloc_energy_virial(pmeGpu);
 838
 839     pme_gpu_copy_common_data_from(pme);
 840
 841     GMX_ASSERT(pmeGpu->common->epsilon_r != 0.0F, "PME GPU: bad electrostatic coefficient");
 842
 843     auto *kernelParamsPtr = pme_gpu_get_kernel_params_base_ptr(pmeGpu);
 844     kernelParamsPtr->constants.elFactor = ONE_4PI_EPS0 / pmeGpu->common->epsilon_r;
 845 }
 846
 847 void pme_gpu_transform_spline_atom_data(const PmeGpu *pmeGpu, const PmeAtomComm *atc,
 848                                         PmeSplineDataType type, int dimIndex, PmeLayoutTransform transform)
 849 {
 850     // The GPU atom spline data is laid out in a different way currently than the CPU one.
 851     // This function converts the data from GPU to CPU layout (in the host memory).
 852     // It is only intended for testing purposes so far.
 853     // Ideally we should use similar layouts on CPU and GPU if we care about mixed modes and their performance
 854     // (e.g. spreading on GPU, gathering on CPU).
 855     GMX_RELEASE_ASSERT(atc->nthread == 1, "Only the serial PME data layout is supported");
 856     const uintmax_t threadIndex  = 0;
 857     const auto      atomCount    = pme_gpu_get_kernel_params_base_ptr(pmeGpu)->atoms.nAtoms;
 858     const auto      atomsPerWarp = pme_gpu_get_atoms_per_warp(pmeGpu);
 859     const auto      pmeOrder     = pmeGpu->common->pme_order;
 860     GMX_ASSERT(pmeOrder == c_pmeGpuOrder, "Only PME order 4 is implemented");
 861
 862     real           *cpuSplineBuffer;
 863     float          *h_splineBuffer;
 864     switch (type)
 865     {
 866         case PmeSplineDataType::Values:
 867             cpuSplineBuffer = atc->spline[threadIndex].theta.coefficients[dimIndex];
 868             h_splineBuffer  = pmeGpu->staging.h_theta;
 869             break;
 870
 871         case PmeSplineDataType::Derivatives:
 872             cpuSplineBuffer = atc->spline[threadIndex].dtheta.coefficients[dimIndex];
 873             h_splineBuffer  = pmeGpu->staging.h_dtheta;
 874             break;
 875
 876         default:
 877             GMX_THROW(gmx::InternalError("Unknown spline data type"));
 878     }
 879
 880     for (auto atomIndex = 0; atomIndex < atomCount; atomIndex++)
 881     {
 882         for (auto orderIndex = 0; orderIndex < pmeOrder; orderIndex++)
 883         {
 884             const auto gpuValueIndex = getSplineParamFullIndex(pmeOrder, orderIndex, dimIndex, atomIndex, atomsPerWarp);
 885             const auto cpuValueIndex = atomIndex * pmeOrder + orderIndex;
 886             GMX_ASSERT(cpuValueIndex < atomCount * pmeOrder, "Atom spline data index out of bounds (while transforming GPU data layout for host)");
 887             switch (transform)
 888             {
 889                 case PmeLayoutTransform::GpuToHost:
 890                     cpuSplineBuffer[cpuValueIndex] = h_splineBuffer[gpuValueIndex];
 891                     break;
 892
 893                 case PmeLayoutTransform::HostToGpu:
 894                     h_splineBuffer[gpuValueIndex] = cpuSplineBuffer[cpuValueIndex];
 895                     break;
 896
 897                 default:
 898                     GMX_THROW(gmx::InternalError("Unknown layout transform"));
 899             }
 900         }
 901     }
 902 }
 903
 904 void pme_gpu_get_real_grid_sizes(const PmeGpu *pmeGpu, gmx::IVec *gridSize, gmx::IVec *paddedGridSize)
 905 {
 906     GMX_ASSERT(gridSize != nullptr, "");
 907     GMX_ASSERT(paddedGridSize != nullptr, "");
 908     GMX_ASSERT(pmeGpu != nullptr, "");
 909     auto *kernelParamsPtr = pme_gpu_get_kernel_params_base_ptr(pmeGpu);
 910     for (int i = 0; i < DIM; i++)
 911     {
 912         (*gridSize)[i]       = kernelParamsPtr->grid.realGridSize[i];
 913         (*paddedGridSize)[i] = kernelParamsPtr->grid.realGridSizePadded[i];
 914     }
 915 }
 916
 917 void pme_gpu_reinit(gmx_pme_t               *pme,
 918                     const gmx_device_info_t *gpuInfo,
 919                     PmeGpuProgramHandle      pmeGpuProgram)
 920 {
 921     if (!pme_gpu_active(pme))
 922     {
 923         return;
 924     }
 925
 926     if (!pme->gpu)
 927     {
 928         /* First-time initialization */
 929         pme_gpu_init(pme, gpuInfo, pmeGpuProgram);
 930     }
 931     else
 932     {
 933         /* After this call nothing in the GPU code should refer to the gmx_pme_t *pme itself - until the next pme_gpu_reinit */
 934         pme_gpu_copy_common_data_from(pme);
 935     }
 936     /* GPU FFT will only get used for a single rank.*/
 937     pme->gpu->settings.performGPUFFT   = (pme->gpu->common->runMode == PmeRunMode::GPU) && !pme_gpu_uses_dd(pme->gpu);
 938     pme->gpu->settings.performGPUSolve = (pme->gpu->common->runMode == PmeRunMode::GPU);
 939
 940     /* Reinit active timers */
 941     pme_gpu_reinit_timings(pme->gpu);
 942
 943     pme_gpu_reinit_grids(pme->gpu);
 944     // Note: if timing the reinit launch overhead becomes more relevant
 945     // (e.g. with regulat PP-PME re-balancing), we should pass wcycle here.
 946     pme_gpu_reinit_computation(pme, nullptr);
 947     /* Clear the previous box - doesn't hurt, and forces the PME CPU recipbox
 948      * update for mixed mode on grid switch. TODO: use shared recipbox field.
 949      */
 950     std::memset(pme->gpu->common->previousBox, 0, sizeof(pme->gpu->common->previousBox));
 951 }
 952
 953 void pme_gpu_destroy(PmeGpu *pmeGpu)
 954 {
 955     /* Free lots of data */
 956     pme_gpu_free_energy_virial(pmeGpu);
 957     pme_gpu_free_bspline_values(pmeGpu);
 958     pme_gpu_free_forces(pmeGpu);
 959     pme_gpu_free_coordinates(pmeGpu);
 960     pme_gpu_free_coefficients(pmeGpu);
 961     pme_gpu_free_spline_data(pmeGpu);
 962     pme_gpu_free_grid_indices(pmeGpu);
 963     pme_gpu_free_fract_shifts(pmeGpu);
 964     pme_gpu_free_grids(pmeGpu);
 965
 966     pme_gpu_destroy_3dfft(pmeGpu);
 967
 968     /* Free the GPU-framework specific data last */
 969     pme_gpu_destroy_specific(pmeGpu);
 970
 971     delete pmeGpu;
 972 }
 973
 974 void pme_gpu_reinit_atoms(PmeGpu *pmeGpu, const int nAtoms, const real *charges)
 975 {
 976     auto      *kernelParamsPtr = pme_gpu_get_kernel_params_base_ptr(pmeGpu);
 977     kernelParamsPtr->atoms.nAtoms = nAtoms;
 978     const int  alignment = pme_gpu_get_atom_data_alignment(pmeGpu);
 979     pmeGpu->nAtomsPadded = ((nAtoms + alignment - 1) / alignment) * alignment;
 980     const int  nAtomsAlloc   = c_usePadding ? pmeGpu->nAtomsPadded : nAtoms;
 981     const bool haveToRealloc = (pmeGpu->nAtomsAlloc < nAtomsAlloc); /* This check might be redundant, but is logical */
 982     pmeGpu->nAtomsAlloc = nAtomsAlloc;
 983
 984 #if GMX_DOUBLE
 985     GMX_RELEASE_ASSERT(false, "Only single precision supported");
 986     GMX_UNUSED_VALUE(charges);
 987 #else
 988     pme_gpu_realloc_and_copy_input_coefficients(pmeGpu, reinterpret_cast<const float *>(charges));
 989     /* Could also be checked for haveToRealloc, but the copy always needs to be performed */
 990 #endif
 991
 992     if (haveToRealloc)
 993     {
 994         pme_gpu_realloc_coordinates(pmeGpu);
 995         pme_gpu_realloc_forces(pmeGpu);
 996         pme_gpu_realloc_spline_data(pmeGpu);
 997         pme_gpu_realloc_grid_indices(pmeGpu);
 998     }
 999 }
1000
1001 void pme_gpu_3dfft(const PmeGpu *pmeGpu, gmx_fft_direction dir, int grid_index)
1002 {
1003     int   timerId = (dir == GMX_FFT_REAL_TO_COMPLEX) ? gtPME_FFT_R2C : gtPME_FFT_C2R;
1004
1005     pme_gpu_start_timing(pmeGpu, timerId);
1006     pmeGpu->archSpecific->fftSetup[grid_index]->perform3dFft(dir, pme_gpu_fetch_timing_event(pmeGpu, timerId));
1007     pme_gpu_stop_timing(pmeGpu, timerId);
1008 }
1009
1010 /*! \brief
1011  * Given possibly large \p blockCount, returns a compact 1D or 2D grid for kernel scheduling,
1012  * to minimize number of unused blocks.
1013  */
1014 std::pair<int, int> inline pmeGpuCreateGrid(const PmeGpu *pmeGpu, int blockCount)
1015 {
1016     // How many maximum widths in X do we need (hopefully just one)
1017     const int minRowCount = (blockCount + pmeGpu->maxGridWidthX - 1) / pmeGpu->maxGridWidthX;
1018     // Trying to make things even
1019     const int colCount = (blockCount + minRowCount - 1) / minRowCount;
1020     GMX_ASSERT((colCount * minRowCount - blockCount) >= 0, "pmeGpuCreateGrid: totally wrong");
1021     GMX_ASSERT((colCount * minRowCount - blockCount) < minRowCount, "pmeGpuCreateGrid: excessive blocks");
1022     return std::pair<int, int>(colCount, minRowCount);
1023 }
1024
1025 void pme_gpu_spread(const PmeGpu    *pmeGpu,
1026                     int gmx_unused   gridIndex,
1027                     real            *h_grid,
1028                     bool             computeSplines,
1029                     bool             spreadCharges)
1030 {
1031     GMX_ASSERT(computeSplines || spreadCharges, "PME spline/spread kernel has invalid input (nothing to do)");
1032     const auto   *kernelParamsPtr = pmeGpu->kernelParams.get();
1033     GMX_ASSERT(kernelParamsPtr->atoms.nAtoms > 0, "No atom data in PME GPU spread");
1034
1035     const size_t blockSize  = pmeGpu->programHandle_->impl_->spreadWorkGroupSize;
1036
1037     const int    order         = pmeGpu->common->pme_order;
1038     GMX_ASSERT(order == c_pmeGpuOrder, "Only PME order 4 is implemented");
1039     const int    atomsPerBlock = blockSize / c_pmeSpreadGatherThreadsPerAtom;
1040     // TODO: pick smaller block size in runtime if needed
1041     // (e.g. on 660 Ti where 50% occupancy is ~25% faster than 100% occupancy with RNAse (~17.8k atoms))
1042     // If doing so, change atomsPerBlock in the kernels as well.
1043     // TODO: test varying block sizes on modern arch-s as well
1044     // TODO: also consider using cudaFuncSetCacheConfig() for preferring shared memory on older architectures
1045     //(for spline data mostly, together with varying PME_GPU_PARALLEL_SPLINE define)
1046     GMX_ASSERT(!c_usePadding || !(c_pmeAtomDataAlignment % atomsPerBlock), "inconsistent atom data padding vs. spreading block size");
1047
1048     const int          blockCount = pmeGpu->nAtomsPadded / atomsPerBlock;
1049     auto               dimGrid    = pmeGpuCreateGrid(pmeGpu, blockCount);
1050
1051     KernelLaunchConfig config;
1052     config.blockSize[0] = config.blockSize[1] = order;
1053     config.blockSize[2] = atomsPerBlock;
1054     config.gridSize[0]  = dimGrid.first;
1055     config.gridSize[1]  = dimGrid.second;
1056     config.stream       = pmeGpu->archSpecific->pmeStream;
1057
1058     int  timingId;
1059     PmeGpuProgramImpl::PmeKernelHandle kernelPtr = nullptr;
1060     if (computeSplines)
1061     {
1062         if (spreadCharges)
1063         {
1064             timingId  = gtPME_SPLINEANDSPREAD;
1065             kernelPtr = pmeGpu->programHandle_->impl_->splineAndSpreadKernel;
1066         }
1067         else
1068         {
1069             timingId  = gtPME_SPLINE;
1070             kernelPtr = pmeGpu->programHandle_->impl_->splineKernel;
1071         }
1072     }
1073     else
1074     {
1075         timingId  = gtPME_SPREAD;
1076         kernelPtr = pmeGpu->programHandle_->impl_->spreadKernel;
1077     }
1078
1079     pme_gpu_start_timing(pmeGpu, timingId);
1080     auto      *timingEvent = pme_gpu_fetch_timing_event(pmeGpu, timingId);
1081 #if c_canEmbedBuffers
1082     const auto kernelArgs = prepareGpuKernelArguments(kernelPtr, config, kernelParamsPtr);
1083 #else
1084     const auto kernelArgs = prepareGpuKernelArguments(kernelPtr, config, kernelParamsPtr,
1085                                                       &kernelParamsPtr->atoms.d_theta,
1086                                                       &kernelParamsPtr->atoms.d_dtheta,
1087                                                       &kernelParamsPtr->atoms.d_gridlineIndices,
1088                                                       &kernelParamsPtr->grid.d_realGrid,
1089                                                       &kernelParamsPtr->grid.d_fractShiftsTable,
1090                                                       &kernelParamsPtr->grid.d_gridlineIndicesTable,
1091                                                       &kernelParamsPtr->atoms.d_coefficients,
1092                                                       &kernelParamsPtr->atoms.d_coordinates
1093                                                       );
1094 #endif
1095
1096     launchGpuKernel(kernelPtr, config, timingEvent, "PME spline/spread", kernelArgs);
1097     pme_gpu_stop_timing(pmeGpu, timingId);
1098
1099     const bool copyBackGrid = spreadCharges && (pme_gpu_is_testing(pmeGpu) || !pme_gpu_performs_FFT(pmeGpu));
1100     if (copyBackGrid)
1101     {
1102         pme_gpu_copy_output_spread_grid(pmeGpu, h_grid);
1103     }
1104     const bool copyBackAtomData = computeSplines && (pme_gpu_is_testing(pmeGpu) || !pme_gpu_performs_gather(pmeGpu));
1105     if (copyBackAtomData)
1106     {
1107         pme_gpu_copy_output_spread_atom_data(pmeGpu);
1108     }
1109 }
1110
1111 void pme_gpu_solve(const PmeGpu *pmeGpu, t_complex *h_grid,
1112                    GridOrdering gridOrdering, bool computeEnergyAndVirial)
1113 {
1114     const bool   copyInputAndOutputGrid = pme_gpu_is_testing(pmeGpu) || !pme_gpu_performs_FFT(pmeGpu);
1115
1116     auto        *kernelParamsPtr = pmeGpu->kernelParams.get();
1117
1118     float       *h_gridFloat = reinterpret_cast<float *>(h_grid);
1119     if (copyInputAndOutputGrid)
1120     {
1121         copyToDeviceBuffer(&kernelParamsPtr->grid.d_fourierGrid, h_gridFloat,
1122                            0, pmeGpu->archSpecific->complexGridSize,
1123                            pmeGpu->archSpecific->pmeStream, pmeGpu->settings.transferKind, nullptr);
1124     }
1125
1126     int majorDim = -1, middleDim = -1, minorDim = -1;
1127     switch (gridOrdering)
1128     {
1129         case GridOrdering::YZX:
1130             majorDim  = YY;
1131             middleDim = ZZ;
1132             minorDim  = XX;
1133             break;
1134
1135         case GridOrdering::XYZ:
1136             majorDim  = XX;
1137             middleDim = YY;
1138             minorDim  = ZZ;
1139             break;
1140
1141         default:
1142             GMX_ASSERT(false, "Implement grid ordering here and below for the kernel launch");
1143     }
1144
1145     const int    maxBlockSize       = pmeGpu->programHandle_->impl_->solveMaxWorkGroupSize;
1146
1147     const int    gridLineSize       = pmeGpu->kernelParams->grid.complexGridSize[minorDim];
1148     const int    gridLinesPerBlock  = std::max(maxBlockSize / gridLineSize, 1);
1149     const int    blocksPerGridLine  = (gridLineSize + maxBlockSize - 1) / maxBlockSize;
1150     int          cellsPerBlock;
1151     if (blocksPerGridLine == 1)
1152     {
1153         cellsPerBlock               = gridLineSize * gridLinesPerBlock;
1154     }
1155     else
1156     {
1157         cellsPerBlock               = (gridLineSize + blocksPerGridLine - 1) / blocksPerGridLine;
1158     }
1159     const int    warpSize           = pmeGpu->programHandle_->impl_->warpSize;
1160     const int    blockSize          = (cellsPerBlock + warpSize - 1) / warpSize * warpSize;
1161
1162     static_assert(GMX_GPU != GMX_GPU_CUDA || c_solveMaxWarpsPerBlock/2 >= 4,
1163                   "The CUDA solve energy kernels needs at least 4 warps. "
1164                   "Here we launch at least half of the max warps.");
1165
1166     KernelLaunchConfig config;
1167     config.blockSize[0] = blockSize;
1168     config.gridSize[0]  = blocksPerGridLine;
1169     // rounding up to full warps so that shuffle operations produce defined results
1170     config.gridSize[1]  = (pmeGpu->kernelParams->grid.complexGridSize[middleDim] + gridLinesPerBlock - 1) / gridLinesPerBlock;
1171     config.gridSize[2]  = pmeGpu->kernelParams->grid.complexGridSize[majorDim];
1172     config.stream       = pmeGpu->archSpecific->pmeStream;
1173
1174     int  timingId = gtPME_SOLVE;
1175     PmeGpuProgramImpl::PmeKernelHandle kernelPtr = nullptr;
1176     if (gridOrdering == GridOrdering::YZX)
1177     {
1178         kernelPtr = computeEnergyAndVirial ?
1179             pmeGpu->programHandle_->impl_->solveYZXEnergyKernel :
1180             pmeGpu->programHandle_->impl_->solveYZXKernel;
1181     }
1182     else if (gridOrdering == GridOrdering::XYZ)
1183     {
1184         kernelPtr = computeEnergyAndVirial ?
1185             pmeGpu->programHandle_->impl_->solveXYZEnergyKernel :
1186             pmeGpu->programHandle_->impl_->solveXYZKernel;
1187     }
1188
1189     pme_gpu_start_timing(pmeGpu, timingId);
1190     auto      *timingEvent = pme_gpu_fetch_timing_event(pmeGpu, timingId);
1191 #if c_canEmbedBuffers
1192     const auto kernelArgs = prepareGpuKernelArguments(kernelPtr, config, kernelParamsPtr);
1193 #else
1194     const auto kernelArgs = prepareGpuKernelArguments(kernelPtr, config, kernelParamsPtr,
1195                                                       &kernelParamsPtr->grid.d_splineModuli,
1196                                                       &kernelParamsPtr->constants.d_virialAndEnergy,
1197                                                       &kernelParamsPtr->grid.d_fourierGrid);
1198 #endif
1199     launchGpuKernel(kernelPtr, config, timingEvent, "PME solve", kernelArgs);
1200     pme_gpu_stop_timing(pmeGpu, timingId);
1201
1202     if (computeEnergyAndVirial)
1203     {
1204         copyFromDeviceBuffer(pmeGpu->staging.h_virialAndEnergy, &kernelParamsPtr->constants.d_virialAndEnergy,
1205                              0, c_virialAndEnergyCount,
1206                              pmeGpu->archSpecific->pmeStream, pmeGpu->settings.transferKind, nullptr);
1207     }
1208
1209     if (copyInputAndOutputGrid)
1210     {
1211         copyFromDeviceBuffer(h_gridFloat, &kernelParamsPtr->grid.d_fourierGrid,
1212                              0, pmeGpu->archSpecific->complexGridSize,
1213                              pmeGpu->archSpecific->pmeStream, pmeGpu->settings.transferKind, nullptr);
1214     }
1215 }
1216
1217 void pme_gpu_gather(PmeGpu                *pmeGpu,
1218                     PmeForceOutputHandling forceTreatment,
1219                     const float           *h_grid,
1220                     bool                   useGpuFPmeReduction
1221                     )
1222 {
1223     /* Copying the input CPU forces for reduction */
1224     if (forceTreatment != PmeForceOutputHandling::Set)
1225     {
1226         pme_gpu_copy_input_forces(pmeGpu);
1227     }
1228
1229     if (!pme_gpu_performs_FFT(pmeGpu) || pme_gpu_is_testing(pmeGpu))
1230     {
1231         pme_gpu_copy_input_gather_grid(pmeGpu, const_cast<float *>(h_grid));
1232     }
1233
1234     if (pme_gpu_is_testing(pmeGpu))
1235     {
1236         pme_gpu_copy_input_gather_atom_data(pmeGpu);
1237     }
1238
1239     const size_t blockSize     = pmeGpu->programHandle_->impl_->gatherWorkGroupSize;
1240     const int    atomsPerBlock = blockSize / c_pmeSpreadGatherThreadsPerAtom;
1241     GMX_ASSERT(!c_usePadding || !(c_pmeAtomDataAlignment % atomsPerBlock), "inconsistent atom data padding vs. gathering block size");
1242
1243     const int          blockCount = pmeGpu->nAtomsPadded / atomsPerBlock;
1244     auto               dimGrid    = pmeGpuCreateGrid(pmeGpu, blockCount);
1245
1246
1247     const int order = pmeGpu->common->pme_order;
1248     GMX_ASSERT(order == c_pmeGpuOrder, "Only PME order 4 is implemented");
1249
1250     KernelLaunchConfig config;
1251     config.blockSize[0] = config.blockSize[1] = order;
1252     config.blockSize[2] = atomsPerBlock;
1253     config.gridSize[0]  = dimGrid.first;
1254     config.gridSize[1]  = dimGrid.second;
1255     config.stream       = pmeGpu->archSpecific->pmeStream;
1256
1257     // TODO test different cache configs
1258
1259     int  timingId = gtPME_GATHER;
1260     // TODO design kernel selection getters and make PmeGpu a friend of PmeGpuProgramImpl
1261     PmeGpuProgramImpl::PmeKernelHandle kernelPtr = (forceTreatment == PmeForceOutputHandling::Set) ?
1262         pmeGpu->programHandle_->impl_->gatherKernel :
1263         pmeGpu->programHandle_->impl_->gatherReduceWithInputKernel;
1264
1265     pme_gpu_start_timing(pmeGpu, timingId);
1266     auto       *timingEvent     = pme_gpu_fetch_timing_event(pmeGpu, timingId);
1267     const auto *kernelParamsPtr = pmeGpu->kernelParams.get();
1268 #if c_canEmbedBuffers
1269     const auto  kernelArgs = prepareGpuKernelArguments(kernelPtr, config, kernelParamsPtr);
1270 #else
1271     const auto  kernelArgs = prepareGpuKernelArguments(kernelPtr, config, kernelParamsPtr,
1272                                                        &kernelParamsPtr->atoms.d_coefficients,
1273                                                        &kernelParamsPtr->grid.d_realGrid,
1274                                                        &kernelParamsPtr->atoms.d_theta,
1275                                                        &kernelParamsPtr->atoms.d_dtheta,
1276                                                        &kernelParamsPtr->atoms.d_gridlineIndices,
1277                                                        &kernelParamsPtr->atoms.d_forces);
1278 #endif
1279     launchGpuKernel(kernelPtr, config, timingEvent, "PME gather", kernelArgs);
1280     pme_gpu_stop_timing(pmeGpu, timingId);
1281
1282     if (useGpuFPmeReduction)
1283     {
1284         pmeGpu->archSpecific->pmeForcesReady.markEvent(pmeGpu->archSpecific->pmeStream);
1285     }
1286     else
1287     {
1288         pme_gpu_copy_output_forces(pmeGpu);
1289     }
1290 }
1291
1292 void * pme_gpu_get_kernelparam_coordinates(const PmeGpu *pmeGpu)
1293 {
1294     if (pmeGpu && pmeGpu->kernelParams)
1295     {
1296         return pmeGpu->kernelParams->atoms.d_coordinates;
1297     }
1298     else
1299     {
1300         return nullptr;
1301     }
1302 }
1303
1304 void * pme_gpu_get_kernelparam_forces(const PmeGpu *pmeGpu)
1305 {
1306     if (pmeGpu && pmeGpu->kernelParams)
1307     {
1308         return pmeGpu->kernelParams->atoms.d_forces;
1309     }
1310     else
1311     {
1312         return nullptr;
1313     }
1314 }
1315
1316 void * pme_gpu_get_stream(const PmeGpu *pmeGpu)
1317 {
1318     if (pmeGpu)
1319     {
1320         return static_cast<void *>(&pmeGpu->archSpecific->pmeStream);
1321     }
1322     else
1323     {
1324         return nullptr;
1325     }
1326 }
1327
1328 GpuEventSynchronizer *pme_gpu_get_forces_ready_synchronizer(const PmeGpu *pmeGpu)
1329 {
1330     if (pmeGpu && pmeGpu->kernelParams)
1331     {
1332         return &pmeGpu->archSpecific->pmeForcesReady;
1333     }
1334     else
1335     {
1336         return nullptr;
1337     }
1338 }