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38 /* The macros in this file are intended to be used for writing
39 * architecture-independent SIMD intrinsics code.
40 * To support a new architecture, adding macros here should be (nearly)
44 #ifdef _gmx_simd_macros_h_
45 #error "gmx_simd_macros.h included twice"
47 #define _gmx_simd_macros_h_
49 /* NOTE: SSE2 acceleration does not include floor or blendv */
52 /* Uncomment the next line, without other SIMD active, for testing plain-C */
53 /* #define GMX_SIMD_REFERENCE_PLAIN_C */
54 #ifdef GMX_SIMD_REFERENCE_PLAIN_C
55 /* Plain C SIMD reference implementation, also serves as documentation */
56 #define GMX_HAVE_SIMD_MACROS
58 /* In general the reference SIMD supports any SIMD width, including 1.
59 * See types/nb_verlet.h for details
61 #define GMX_SIMD_REF_WIDTH 4
63 /* Include plain-C reference implementation, also serves as documentation */
64 #include "gmx_simd_ref.h"
66 #define GMX_SIMD_WIDTH_HERE GMX_SIMD_REF_WIDTH
68 /* float/double SIMD register type */
69 #define gmx_mm_pr gmx_simd_ref_pr
71 /* boolean SIMD register type */
72 #define gmx_mm_pb gmx_simd_ref_pb
74 /* integer SIMD register type, only for table indexing and exclusion masks */
75 #define gmx_epi32 gmx_simd_ref_epi32
76 #define GMX_SIMD_EPI32_WIDTH GMX_SIMD_REF_EPI32_WIDTH
78 /* Load GMX_SIMD_WIDTH_HERE reals for memory starting at r */
79 #define gmx_load_pr gmx_simd_ref_load_pr
80 /* Set all SIMD register elements to *r */
81 #define gmx_load1_pr gmx_simd_ref_load1_pr
82 #define gmx_set1_pr gmx_simd_ref_set1_pr
83 #define gmx_setzero_pr gmx_simd_ref_setzero_pr
84 #define gmx_store_pr gmx_simd_ref_store_pr
86 #define gmx_add_pr gmx_simd_ref_add_pr
87 #define gmx_sub_pr gmx_simd_ref_sub_pr
88 #define gmx_mul_pr gmx_simd_ref_mul_pr
89 /* For the FMA macros below, aim for c=d in code, so FMA3 uses 1 instruction */
90 #define gmx_madd_pr gmx_simd_ref_madd_pr
91 #define gmx_nmsub_pr gmx_simd_ref_nmsub_pr
93 #define gmx_max_pr gmx_simd_ref_max_pr
94 #define gmx_blendzero_pr gmx_simd_ref_blendzero_pr
96 #define gmx_round_pr gmx_simd_ref_round_pr
98 /* Not required, only used to speed up the nbnxn tabulated PME kernels */
99 #define GMX_SIMD_HAVE_FLOOR
100 #ifdef GMX_SIMD_HAVE_FLOOR
101 #define gmx_floor_pr gmx_simd_ref_floor_pr
104 /* Not required, only used when blendv is faster than comparison */
105 #define GMX_SIMD_HAVE_BLENDV
106 #ifdef GMX_SIMD_HAVE_BLENDV
107 #define gmx_blendv_pr gmx_simd_ref_blendv_pr
110 /* Copy the sign of a to b, assumes b >= 0 for efficiency */
111 #define gmx_cpsgn_nonneg_pr gmx_simd_ref_cpsgn_nonneg_pr
113 /* Very specific operation required in the non-bonded kernels */
114 #define gmx_masknot_add_pr gmx_simd_ref_masknot_add_pr
117 #define gmx_cmplt_pr gmx_simd_ref_cmplt_pr
119 /* Logical operations on SIMD booleans */
120 #define gmx_and_pb gmx_simd_ref_and_pb
121 #define gmx_or_pb gmx_simd_ref_or_pb
123 /* Returns a single int (0/1) which tells if any of the 4 booleans is True */
124 #define gmx_anytrue_pb gmx_simd_ref_anytrue_pb
126 /* Conversions only used for PME table lookup */
127 #define gmx_cvttpr_epi32 gmx_simd_ref_cvttpr_epi32
128 #define gmx_cvtepi32_pr gmx_simd_ref_cvtepi32_pr
130 /* These two function only need to be approximate, Newton-Raphson iteration
131 * is used for full accuracy in gmx_invsqrt_pr and gmx_inv_pr.
133 #define gmx_rsqrt_pr gmx_simd_ref_rsqrt_pr
134 #define gmx_rcp_pr gmx_simd_ref_rcp_pr
136 /* sqrt+inv+sin+cos+acos+atan2 are used for bonded potentials, exp for PME */
137 #define GMX_SIMD_HAVE_EXP
138 #ifdef GMX_SIMD_HAVE_EXP
139 #define gmx_exp_pr gmx_simd_ref_exp_pr
141 #define GMX_SIMD_HAVE_TRIGONOMETRIC
142 #ifdef GMX_SIMD_HAVE_TRIGONOMETRIC
143 #define gmx_sqrt_pr gmx_simd_ref_sqrt_pr
144 #define gmx_sincos_pr gmx_simd_ref_sincos_pr
145 #define gmx_acos_pr gmx_simd_ref_acos_pr
146 #define gmx_atan2_pr gmx_simd_ref_atan2_pr
149 #endif /* GMX_SIMD_REFERENCE_PLAIN_C */
152 /* The same SIMD macros can be translated to SIMD intrinsics (and compiled
153 * to instructions for) different SIMD width and float precision.
155 * On x86: The gmx_ prefix is replaced by _mm_ or _mm256_ (SSE or AVX).
156 * The _pr suffix is replaced by _ps or _pd (for single or double precision).
157 * Compiler settings will decide if 128-bit intrinsics will
158 * be translated into SSE or AVX instructions.
162 #ifdef GMX_USE_HALF_WIDTH_SIMD_HERE
163 #if defined GMX_X86_AVX_256
164 /* We have half SIMD width support, continue */
166 #error "half SIMD width intrinsics are not supported"
172 /* This is for general x86 SIMD instruction sets that also support SSE2 */
173 #define GMX_HAVE_SIMD_MACROS
175 /* Include the highest supported x86 SIMD intrisics + math functions */
176 #ifdef GMX_X86_AVX_256
177 #include "gmx_x86_avx_256.h"
179 #include "gmx_math_x86_avx_256_double.h"
181 #include "gmx_math_x86_avx_256_single.h"
184 #ifdef GMX_X86_AVX_128_FMA
185 #include "gmx_x86_avx_128_fma.h"
187 #include "gmx_math_x86_avx_128_fma_double.h"
189 #include "gmx_math_x86_avx_128_fma_single.h"
192 #ifdef GMX_X86_SSE4_1
193 #include "gmx_x86_sse4_1.h"
195 #include "gmx_math_x86_sse4_1_double.h"
197 #include "gmx_math_x86_sse4_1_single.h"
201 #include "gmx_x86_sse2.h"
203 #include "gmx_math_x86_sse2_double.h"
205 #include "gmx_math_x86_sse2_single.h"
208 #error No x86 acceleration defined
213 /* exp and trigonometric functions are included above */
214 #define GMX_SIMD_HAVE_EXP
215 #define GMX_SIMD_HAVE_TRIGONOMETRIC
217 #if !defined GMX_X86_AVX_256 || defined GMX_USE_HALF_WIDTH_SIMD_HERE
221 #define GMX_SIMD_WIDTH_HERE 4
223 #define gmx_mm_pr __m128
225 #define gmx_mm_pb __m128
227 #define gmx_epi32 __m128i
228 #define GMX_SIMD_EPI32_WIDTH 4
230 #define gmx_load_pr _mm_load_ps
231 #define gmx_load1_pr _mm_load1_ps
232 #define gmx_set1_pr _mm_set1_ps
233 #define gmx_setzero_pr _mm_setzero_ps
234 #define gmx_store_pr _mm_store_ps
236 #define gmx_add_pr _mm_add_ps
237 #define gmx_sub_pr _mm_sub_ps
238 #define gmx_mul_pr _mm_mul_ps
239 #ifdef GMX_X86_AVX_128_FMA
240 #define GMX_SIMD_HAVE_FMA
241 #define gmx_madd_pr(a, b, c) _mm_macc_ps(a, b, c)
242 #define gmx_nmsub_pr(a, b, c) _mm_nmacc_ps(a, b, c)
244 #define gmx_madd_pr(a, b, c) _mm_add_ps(c, _mm_mul_ps(a, b))
245 #define gmx_nmsub_pr(a, b, c) _mm_sub_ps(c, _mm_mul_ps(a, b))
247 #define gmx_max_pr _mm_max_ps
248 #define gmx_blendzero_pr _mm_and_ps
250 #define gmx_cmplt_pr _mm_cmplt_ps
251 #define gmx_and_pb _mm_and_ps
252 #define gmx_or_pb _mm_or_ps
254 #ifdef GMX_X86_SSE4_1
255 #define gmx_round_pr(x) _mm_round_ps(x, 0x0)
256 #define GMX_SIMD_HAVE_FLOOR
257 #define gmx_floor_pr _mm_floor_ps
259 #define gmx_round_pr(x) _mm_cvtepi32_ps(_mm_cvtps_epi32(x))
262 #ifdef GMX_X86_SSE4_1
263 #define GMX_SIMD_HAVE_BLENDV
264 #define gmx_blendv_pr _mm_blendv_ps
267 static gmx_inline gmx_mm_pr gmx_cpsgn_nonneg_pr(gmx_mm_pr a, gmx_mm_pr b)
269 /* The value -0.0 has only the sign-bit set */
270 gmx_mm_pr sign_mask = _mm_set1_ps(-0.0);
271 return _mm_or_ps(_mm_and_ps(a, sign_mask), b);
274 static gmx_inline gmx_mm_pr gmx_masknot_add_pr(gmx_mm_pb a, gmx_mm_pr b, gmx_mm_pr c) { return _mm_add_ps(b, _mm_andnot_ps(a, c)); };
276 #define gmx_anytrue_pb _mm_movemask_ps
278 #define gmx_cvttpr_epi32 _mm_cvttps_epi32
279 #define gmx_cvtepi32_pr _mm_cvtepi32_ps
281 #define gmx_rsqrt_pr _mm_rsqrt_ps
282 #define gmx_rcp_pr _mm_rcp_ps
284 #define gmx_exp_pr gmx_mm_exp_ps
285 #define gmx_sqrt_pr gmx_mm_sqrt_ps
286 #define gmx_sincos_pr gmx_mm_sincos_ps
287 #define gmx_acos_pr gmx_mm_acos_ps
288 #define gmx_atan2_pr gmx_mm_atan2_ps
290 #else /* ifndef GMX_DOUBLE */
292 #define GMX_SIMD_WIDTH_HERE 2
294 #define gmx_mm_pr __m128d
296 #define gmx_mm_pb __m128d
298 #define gmx_epi32 __m128i
299 #define GMX_SIMD_EPI32_WIDTH 4
301 #define gmx_load_pr _mm_load_pd
302 #define gmx_load1_pr _mm_load1_pd
303 #define gmx_set1_pr _mm_set1_pd
304 #define gmx_setzero_pr _mm_setzero_pd
305 #define gmx_store_pr _mm_store_pd
307 #define gmx_add_pr _mm_add_pd
308 #define gmx_sub_pr _mm_sub_pd
309 #define gmx_mul_pr _mm_mul_pd
310 #ifdef GMX_X86_AVX_128_FMA
311 #define GMX_SIMD_HAVE_FMA
312 #define gmx_madd_pr(a, b, c) _mm_macc_pd(a, b, c)
313 #define gmx_nmsub_pr(a, b, c) _mm_nmacc_pd(a, b, c)
315 #define gmx_madd_pr(a, b, c) _mm_add_pd(c, _mm_mul_pd(a, b))
316 #define gmx_nmsub_pr(a, b, c) _mm_sub_pd(c, _mm_mul_pd(a, b))
318 #define gmx_max_pr _mm_max_pd
319 #define gmx_blendzero_pr _mm_and_pd
321 #ifdef GMX_X86_SSE4_1
322 #define gmx_round_pr(x) _mm_round_pd(x, 0x0)
323 #define GMX_SIMD_HAVE_FLOOR
324 #define gmx_floor_pr _mm_floor_pd
326 #define gmx_round_pr(x) _mm_cvtepi32_pd(_mm_cvtpd_epi32(x))
327 /* gmx_floor_pr is not used in code for pre-SSE4_1 hardware */
330 #ifdef GMX_X86_SSE4_1
331 #define GMX_SIMD_HAVE_BLENDV
332 #define gmx_blendv_pr _mm_blendv_pd
335 static gmx_inline gmx_mm_pr gmx_cpsgn_nonneg_pr(gmx_mm_pr a, gmx_mm_pr b)
337 gmx_mm_pr sign_mask = _mm_set1_pd(-0.0);
338 return _mm_or_pd(_mm_and_pd(a, sign_mask), b);
341 static gmx_inline gmx_mm_pr gmx_masknot_add_pr(gmx_mm_pb a, gmx_mm_pr b, gmx_mm_pr c) { return _mm_add_pd(b, _mm_andnot_pd(a, c)); };
343 #define gmx_cmplt_pr _mm_cmplt_pd
345 #define gmx_and_pb _mm_and_pd
346 #define gmx_or_pb _mm_or_pd
348 #define gmx_anytrue_pb _mm_movemask_pd
350 #define gmx_cvttpr_epi32 _mm_cvttpd_epi32
351 #define gmx_cvtepi32_pr _mm_cvtepi32_pd
353 #define gmx_rsqrt_pr(r) _mm_cvtps_pd(_mm_rsqrt_ps(_mm_cvtpd_ps(r)))
354 #define gmx_rcp_pr(r) _mm_cvtps_pd(_mm_rcp_ps(_mm_cvtpd_ps(r)))
356 #define gmx_exp_pr gmx_mm_exp_pd
357 #define gmx_sqrt_pr gmx_mm_sqrt_pd
358 #define gmx_sincos_pr gmx_mm_sincos_pd
359 #define gmx_acos_pr gmx_mm_acos_pd
360 #define gmx_atan2_pr gmx_mm_atan2_pd
362 #endif /* ifndef GMX_DOUBLE */
365 /* We have GMX_X86_AVX_256 and not GMX_USE_HALF_WIDTH_SIMD_HERE,
366 * so we use 256-bit SIMD.
371 #define GMX_SIMD_WIDTH_HERE 8
373 #define gmx_mm_pr __m256
375 #define gmx_mm_pb __m256
377 #define gmx_epi32 __m256i
378 #define GMX_SIMD_EPI32_WIDTH 8
380 #define gmx_load_pr _mm256_load_ps
381 #define gmx_load1_pr(x) _mm256_set1_ps((x)[0])
382 #define gmx_set1_pr _mm256_set1_ps
383 #define gmx_setzero_pr _mm256_setzero_ps
384 #define gmx_store_pr _mm256_store_ps
386 #define gmx_add_pr _mm256_add_ps
387 #define gmx_sub_pr _mm256_sub_ps
388 #define gmx_mul_pr _mm256_mul_ps
389 #define gmx_madd_pr(a, b, c) _mm256_add_ps(c, _mm256_mul_ps(a, b))
390 #define gmx_nmsub_pr(a, b, c) _mm256_sub_ps(c, _mm256_mul_ps(a, b))
391 #define gmx_max_pr _mm256_max_ps
392 #define gmx_blendzero_pr _mm256_and_ps
394 #define gmx_round_pr(x) _mm256_round_ps(x, 0x0)
395 #define GMX_SIMD_HAVE_FLOOR
396 #define gmx_floor_pr _mm256_floor_ps
398 #define GMX_SIMD_HAVE_BLENDV
399 #define gmx_blendv_pr _mm256_blendv_ps
401 static gmx_inline gmx_mm_pr gmx_cpsgn_nonneg_pr(gmx_mm_pr a, gmx_mm_pr b)
403 gmx_mm_pr sign_mask = _mm256_set1_ps(-0.0);
404 return _mm256_or_ps(_mm256_and_ps(a, sign_mask), b);
407 static gmx_inline gmx_mm_pr gmx_masknot_add_pr(gmx_mm_pb a, gmx_mm_pr b, gmx_mm_pr c) { return _mm256_add_ps(b, _mm256_andnot_ps(a, c)); };
409 /* Less-than (we use ordered, non-signaling, but that's not required) */
410 #define gmx_cmplt_pr(x, y) _mm256_cmp_ps(x, y, 0x11)
411 #define gmx_and_pb _mm256_and_ps
412 #define gmx_or_pb _mm256_or_ps
414 #define gmx_anytrue_pb _mm256_movemask_ps
416 #define gmx_cvttpr_epi32 _mm256_cvttps_epi32
418 #define gmx_rsqrt_pr _mm256_rsqrt_ps
419 #define gmx_rcp_pr _mm256_rcp_ps
421 #define gmx_exp_pr gmx_mm256_exp_ps
422 #define gmx_sqrt_pr gmx_mm256_sqrt_ps
423 #define gmx_sincos_pr gmx_mm256_sincos_ps
424 #define gmx_acos_pr gmx_mm256_acos_ps
425 #define gmx_atan2_pr gmx_mm256_atan2_ps
427 #else /* ifndef GMX_DOUBLE */
429 #define GMX_SIMD_WIDTH_HERE 4
431 #define gmx_mm_pr __m256d
433 #define gmx_mm_pb __m256d
435 /* We use 128-bit integer registers because of missing 256-bit operations */
436 #define gmx_epi32 __m128i
437 #define GMX_SIMD_EPI32_WIDTH 4
439 #define gmx_load_pr _mm256_load_pd
440 #define gmx_load1_pr(x) _mm256_set1_pd((x)[0])
441 #define gmx_set1_pr _mm256_set1_pd
442 #define gmx_setzero_pr _mm256_setzero_pd
443 #define gmx_store_pr _mm256_store_pd
445 #define gmx_add_pr _mm256_add_pd
446 #define gmx_sub_pr _mm256_sub_pd
447 #define gmx_mul_pr _mm256_mul_pd
448 #define gmx_madd_pr(a, b, c) _mm256_add_pd(c, _mm256_mul_pd(a, b))
449 #define gmx_nmsub_pr(a, b, c) _mm256_sub_pd(c, _mm256_mul_pd(a, b))
450 #define gmx_max_pr _mm256_max_pd
451 #define gmx_blendzero_pr _mm256_and_pd
453 #define gmx_round_pr(x) _mm256_round_pd(x, 0x0)
454 #define GMX_SIMD_HAVE_FLOOR
455 #define gmx_floor_pr _mm256_floor_pd
457 #define GMX_SIMD_HAVE_BLENDV
458 #define gmx_blendv_pr _mm256_blendv_pd
460 static gmx_inline gmx_mm_pr gmx_cpsgn_nonneg_pr(gmx_mm_pr a, gmx_mm_pr b)
462 gmx_mm_pr sign_mask = _mm256_set1_pd(-0.0);
463 return _mm256_or_pd(_mm256_and_pd(a, sign_mask), b);
466 static gmx_inline gmx_mm_pr gmx_masknot_add_pr(gmx_mm_pb a, gmx_mm_pr b, gmx_mm_pr c) { return _mm256_add_pd(b, _mm256_andnot_pd(a, c)); };
468 /* Less-than (we use ordered, non-signaling, but that's not required) */
469 #define gmx_cmplt_pr(x, y) _mm256_cmp_pd(x, y, 0x11)
471 #define gmx_and_pb _mm256_and_pd
472 #define gmx_or_pb _mm256_or_pd
474 #define gmx_anytrue_pb _mm256_movemask_pd
476 #define gmx_cvttpr_epi32 _mm256_cvttpd_epi32
478 #define gmx_rsqrt_pr(r) _mm256_cvtps_pd(_mm_rsqrt_ps(_mm256_cvtpd_ps(r)))
479 #define gmx_rcp_pr(r) _mm256_cvtps_pd(_mm_rcp_ps(_mm256_cvtpd_ps(r)))
481 #define gmx_exp_pr gmx_mm256_exp_pd
482 #define gmx_sqrt_pr gmx_mm256_sqrt_pd
483 #define gmx_sincos_pr gmx_mm256_sincos_pd
484 #define gmx_acos_pr gmx_mm256_acos_pd
485 #define gmx_atan2_pr gmx_mm256_atan2_pd
487 #endif /* ifndef GMX_DOUBLE */
489 #endif /* 128- or 256-bit x86 SIMD */
491 #endif /* GMX_X86_SSE2 */
494 #ifdef GMX_HAVE_SIMD_MACROS
495 /* Generic functions to extract a SIMD aligned pointer from a pointer x.
496 * x should have at least GMX_SIMD_WIDTH_HERE elements extra compared
497 * to how many you want to use, to avoid indexing outside the aligned region.
500 static gmx_inline real *
501 gmx_simd_align_real(const real *x)
503 return (real *)(((size_t)((x)+GMX_SIMD_WIDTH_HERE)) & (~((size_t)(GMX_SIMD_WIDTH_HERE*sizeof(real)-1))));
506 static gmx_inline int *
507 gmx_simd_align_int(const int *x)
509 return (int *)(((size_t)((x)+GMX_SIMD_WIDTH_HERE)) & (~((size_t)(GMX_SIMD_WIDTH_HERE*sizeof(int )-1))));
513 /* Include the math functions which only need the above macros,
514 * generally these are the ones that don't need masking operations.
517 #include "gmx_simd_math_double.h"
519 #include "gmx_simd_math_single.h"
522 #endif /* GMX_HAVE_SIMD_MACROS */
524 #endif /* _gmx_simd_macros_h_ */